Postmetallization annealing effect of TiN-gate Ge metal-oxide-semiconductor capacitor with ultrathin SiO2/GeO2 bilayer passivation

Nakashima, Hiroshi; Iwamura, Yoshiaki; Sakamoto, Kazumitsu; Wang, Dong; Hirayama, Kana; Yamamoto, Keisuke; Yang, Hsiharng

doi:10.1063/1.3601480

Cited by 25 publications

(19 citation statements)

References 11 publications

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“…Positive shifts in the flatband voltage with nitrogen, forming gas, or oxygen annealing have been reported for Ge MOS capacitors passivated with GeON, 16 Al 2 O 3 , 17 HfO 2 , 18 and a SiO 2 /GeO 2 bilayer. 19 These results are consistent with theoretical calculations that dangling bonds in Ge are always negatively charged 20 at the Ge/ dielectric interface and that an anneal increases the number of dangling bonds. Using the Berglund method, 21 the D it of the devices in this work was found to be in the 2 À 4 Â 10 12 cm À2 eV À1 range at the flatband voltage.…”

supporting

confidence: 90%

Impact of post-metallization annealing on Ge-on-Si photodiodes passivated with silicon dioxide

DiLello¹,

Hoyt²

2011

Applied Physics Letters

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Ge-on-Si photodiodes were fabricated from epitaxial germanium films grown by low-pressure chemical vapor deposition. These vertical p-i-n diodes were passivated with SiO2 deposited by chemical vapor deposition. It is found that the incorporation of a post-metallization anneal reduces the dark current by 1000X for small-area devices, with 10 × 10 μm diodes exhibiting a dark current of 8 nA at −1 V. Metal-oxide-semiconductor capacitors were also fabricated using the same materials and annealing conditions. Capacitance-voltage measurements indicate that the anneal changes the surface condition of the germanium from depletion to accumulation, lowering the photodiode perimeter leakage current.

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supporting

confidence: 90%

Impact of post-metallization annealing on Ge-on-Si photodiodes passivated with silicon dioxide

DiLello¹,

Hoyt²

2011

Applied Physics Letters

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“…The nature of these instabilities is still matter of debate. Instabilities can be related to transition currents [12,13], dielectric relaxation current [14,15], dipole formation at the high-k/SiO 2 interface [16], Maxwell-Wagner instability in bilayer dielectric stacks [17] and trapping of electrons or holes on various types of traps [18,19]. Although some attempts were made to explain all these phenomena with a unified model, as due to the bilayer structure itself of the high-k dielectrics [20], it appears that the mechanisms affecting the instabilities depend on the specific high-k dielectric composition and fabrication conditions.…”

Section: Introductionmentioning

confidence: 99%

HYSTERESIS-LIKE FLATBAND VOLTAGE INSTABILITIES IN Al/Ta2O5-SiO2/Si STRUCTURES AND THEIR CONNECTION WITH J-V CHARACTERISTICS

Novkovski¹,

Paskaleva²,

Atanassova³

2017

Contributions

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Flatband and current-voltage instabilities in unstressed Al/Ta 2 O 5 -SiO 2 /Si structures were studied in details. It has been found that, after an initial run left on fresh samples, both C-V and J-V characteristics exhibit repeatable patterns. Precisely repeatable counterclockwise hysteresis-like loop in C-V characteristics occurs, while no significant hysteretic behaviour is observed in static J-V characteristics. The reduced instability in J-V characteristics is explained by mutual compensation of two opposite effects owing to the presence of trapped positive charges on slow traps in the interfacial SiO 2 -like layer: (i) flatband voltage shift and (ii) lowering of Fowler-Nordheim tunnelling barrier for holes injected from the Si substrate. Correct determination of equivalent oxide thickness and fast interface state densities requires using the C-V curves obtained during the runs right, because progressive trapping on slow states occurs during the runs left. Value of the oxide charge is to be determined using the value of the flatband voltage obtained from the run left (after an initial run right), since it corresponds to the state of empty slow traps.

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“…8(a), (b), and (c) are labeled to as A, B and C, respectively. (2,12). Thus, the passivation method for sample C cannot be used from a view point of device isolation.…”

Section: S/d Junction Formation For N-and P-mosfetsmentioning

confidence: 96%

(Invited) Gate Stack and Source/Drain Junction Formations for High-Mobility Ge MOSFETs

Nakashima

Yamamoto

Yang³

et al. 2013

ECS Trans.

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Ge is of great interest as a candidate channel material for future CMOS devices due to its high intrinsic carrier mobility. To translate this potential into CMOS, high-quality gate-stack and source/drain (S/D) junction formations are essential. We fabricated Ge n-and p-MOSFETs using the gate-stack formation by bilayer (SiO 2 /GeO 2 ) passivation and using S/D junction formations by thermal diffusion of P and ion implantation of B. The electron and hole channel mobilities of the fabricated MOSFETs were 1097 and 376 cm 2 V -1 s -1 , respectively, despite the very thin GeO 2 thickness. We will present the detailed fabrication method and device performance.

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Postmetallization annealing effect of TiN-gate Ge metal-oxide-semiconductor capacitor with ultrathin SiO2/GeO2 bilayer passivation

Cited by 25 publications

References 11 publications

Impact of post-metallization annealing on Ge-on-Si photodiodes passivated with silicon dioxide

Impact of post-metallization annealing on Ge-on-Si photodiodes passivated with silicon dioxide

HYSTERESIS-LIKE FLATBAND VOLTAGE INSTABILITIES IN Al/Ta2O5-SiO2/Si STRUCTURES AND THEIR CONNECTION WITH J-V CHARACTERISTICS

(Invited) Gate Stack and Source/Drain Junction Formations for High-Mobility Ge MOSFETs

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