2006 International Symposium on VLSI Design, Automation and Test 2006
DOI: 10.1109/vdat.2006.258174
|View full text |Cite
|
Sign up to set email alerts
|

Power-On Current Control In Sleep Transistor Implementations

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
3
1
1

Citation Types

0
5
0

Year Published

2008
2008
2012
2012

Publication Types

Select...
5
2

Relationship

0
7

Authors

Journals

citations
Cited by 7 publications
(5 citation statements)
references
References 5 publications
0
5
0
Order By: Relevance
“…Howard and Shi proposed reducing inrush current by splitting the chip into logic rows, each powered up by one or few sleep transistors [10], with a controller to stagger their turn on. They also proposed a two-stage power-on method as an alternative solution.…”
Section: Previous Workmentioning
confidence: 99%
See 2 more Smart Citations
“…Howard and Shi proposed reducing inrush current by splitting the chip into logic rows, each powered up by one or few sleep transistors [10], with a controller to stagger their turn on. They also proposed a two-stage power-on method as an alternative solution.…”
Section: Previous Workmentioning
confidence: 99%
“…The above mentioned solutions in [14,10,22,6] are suitable for handling inrush current for designs where the functional blocks are known beforehand. Unlike ASICs, FPGAs are configurable, and they need a solution that is suitable to a wide range of applications.…”
Section: Previous Workmentioning
confidence: 99%
See 1 more Smart Citation
“…The critical issue in on/off policy is to find the optimal tradeoff between these two contrasting requirements. The problem was firstly considered in [18], which proposed two different structures to control the rush current, a non-uniform sized parallel STs and gate-voltage-controlled staircase-ST. A dual daisy chain structure was proposed in [19] which use a weak chain to trickle the charge, and use the main chain to work under active mode to maintain the performance. Another technique [20] employs an auxiliary power network and extra bypass switches such that the power or ground fluctuation does not affect nearby active circuits that are connected to the other power network.…”
Section: On/off Policy and Power/ground Bounce Suppressmentioning
confidence: 99%
“…In addition, no information is given in the paper concerning the approach followed for sizing the transistors. Details on sizing are provided in [6], but unfortunately only a case study is discussed in this paper, and no systematic approach is considered. The second structure presented in [5], shown in Figure 4, is a gate voltage controlled architecture (i.e., staircase-ST ).…”
Section: Previous Workmentioning
confidence: 99%