Practical implementation of defect-oriented testing for a mixed-signal class-D amplifier

Beurze, R.H.; Xing, Yizi; Kleef, R. van; Tangelder, R.J.W.T.; Engin, N.

doi:10.1109/etw.1999.804205

Cited by 10 publications

(5 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…They encapsulate tools (e.g., fault extractor or analogue simulator) and facilitate execution of the DOT flow [17] [18]. We use NXP's internal tool DOTSS (defect oriented test simulation system) in this work [19]. Reducing production test size has been studied in [20] where analogue fault modeling is discussed followed by an analysis of specification tests and algorithms for fault-driven test selection.…”

Section: Previous Workmentioning

confidence: 99%

Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example

Hashempour

Dohmen

Tasic

et al. 2011

2011 Design, Automation &Amp; Test in Europe

View full text Add to dashboard Cite

We present an application of Defect Oriented Testing (DOT 1 ) to an industrial mixed signal device to reduce test time and maintain quality. The device is an automotive IC product with stringent quality requirements and a mature test program that is already in volume production. A complete flow is presented including defect extraction, defect simulation, test selection, and validation. A major challenge of DOT for mixed signal devices is the simulation time. We address this challenge with a new fault simulation algorithm that provides significant speedup in the DOT process. Based on the fault simulations, we determine a minimal set of tests which detects all defects. The proposed minimal test set is compared with the actual test results of more than a million ICs. We prove that the production tests of the device can be reduced by at least 35%.

show abstract

Section: Previous Workmentioning

confidence: 99%

Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example

Hashempour

Dohmen

Tasic

et al. 2011

2011 Design, Automation &Amp; Test in Europe

View full text Add to dashboard Cite

show abstract

“…Defect models used in literature are usually small resistances for shorts and very large resistances for open circuits [7], [8], [6]. Although simple, most of the time these models may not provide the desired accuracy to observe the true behavior of the defects.…”

Section: A Defect Modelmentioning

confidence: 99%

“…Physical defects have typically been modeled with extremely simplistic circuit behavior [6], [7], [8] , namely as open and short catastrophic defects having a fixed resistance value typically on the order of 1MΩ and 1Ω respectively [7]. Presently, more sophisticated models of various defects have been proposed in [9], where S-parameters of defects are extracted using an electromagnetic simulator.…”

Section: Introductionmentioning

confidence: 99%

“…In order to calculate defect occurrence probability of this defect we need size information of the defect. Various defect size distributions have been proposed [6]. We use the defect distribution model presented in [14], as shown in Figure 2, while the probability distribution curve given in [14], [6].…”

Section: Introductionmentioning

confidence: 99%

“…Various defect size distributions have been proposed [6]. We use the defect distribution model presented in [14], as shown in Figure 2, while the probability distribution curve given in [14], [6]. r 0 is a parameter of the curve; it is usually taken as the minimum feature length of the process.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Defect-based test optimization for analog/RF circuits for near-zero DPPM applications

Yılmaz

Ozev

2009

2009 IEEE International Conference on Computer Design

View full text Add to dashboard Cite

Abstract-Analog circuits are often tested based on their specifications. While specification-based testing ensures the initial product quality, full testing is often not possible in high volume production. Moreover, even full specification-based testing cannot guarantee that the circuit does not contain any physical defects. Some application domains require near-zero defect levels independent of whether the specifications are met. In this work, we present a defect based test optimization method focusing on defective parts per million (DPPM) minimization. We extract potential defects through inductive fault analysis (IFA) and reduce the number of tests without degrading the test quality. In order to achieve near zero DPPM, we employ outlier analysis to identify defective circuits that cannot be identified using specification based methods. Simulation results on an LNA show that DPPM is reduced down to 0 at a cost of 0.2% yield loss with the proposed method.

show abstract

Short circuit faults in state-of-the-art ADCs - are they hard or soft?

Lechner

Richardson²,

Hermes³

Proceedings 10th Asian Test Symposium

View full text Add to dashboard Cite

Practical implementation of defect-oriented testing for a mixed-signal class-D amplifier

Cited by 10 publications

References 17 publications

Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example

Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example

Defect-based test optimization for analog/RF circuits for near-zero DPPM applications

Short circuit faults in state-of-the-art ADCs - are they hard or soft?

Contact Info

Product

Resources

About