Predicting substrate-induced focus error

Liegl, Bernhard; Sapp, Brian; Greco, S.; Brunner, Timothy A.; Felix, Nelson; Stobert, Ian; Nafisi, Kourosh; Sarma, Chandrasekhar

doi:10.1117/1.3530580

Cited by 5 publications

(1 citation statement)

References 3 publications

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“…This metric is an approximation of measuring deviations after lithographic tools implement an automated fix as described inLiegl et al [2010].…”

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confidence: 99%

An Effective Chemical Mechanical Polishing Fill Insertion Approach

Liu

et al. 2016

ACM Trans. Des. Autom. Electron. Syst.

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To reduce chip-scale topography variation, dummy fill is commonly used to improve the layout density uniformity. Previous works either sought the most uniform density distribution or sought to minimize the inserted dummy fills while satisfying certain density uniformity constraint. However, due to more stringent manufacturing challenges, more criteria, like line deviation and outlier, emerge at newer technology nodes. This article presents a joint optimization scheme to consider variation, total fill, line deviation, outlier, overlap, and running time simultaneously. More specifically, first we decompose the rectilinear polygons and partition fillable regions into rectangles for easier processing. After decomposition, we insert dummy fills into the fillable rectangular regions optimizing the fill metrics simultaneously. We propose three approaches, Fast Median approach, LP approach, and Iterative approach, which are much faster with better quality, compared with the results of the top three contestants in the ICCAD Contest 2014.

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“…This metric is an approximation of measuring deviations after lithographic tools implement an automated fix as described inLiegl et al [2010].…”

mentioning

confidence: 99%

An Effective Chemical Mechanical Polishing Fill Insertion Approach

Liu

et al. 2016

ACM Trans. Des. Autom. Electron. Syst.

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Monitoring process-induced focus errors using high-resolution flatness metrology

Morgenfeld

Brunner

Nummy

et al. 2015

2015 26th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)

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Reducing focus errors during optical lithography patterning is crucial for minimizing defects and for achieving the desired critical dimension uniformity (CDU). Factors that contribute to lithography defocus originate from both within and outside the exposure tools. Wafer geometry and topography have been shown to be a major contributor to the focus budget, but decoupling wafer issues from scanner tooling / chuck signatures is far from trivial. In this paper we will review how the use of flatness metrology in a 22nm manufacturing environment improved our ability to measure focus errors as well as enabled the decoupling of error between tooling and wafer sources. We will also review several examples of experimental datasets demonstrating how this wafer shape measurement technique has provided unique insight to the nature of topography based focus error, as well as provide a valuable learning mechanism for driving improvement in process cycles of learning.

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ICCAD-2014 CAD contest in design for manufacturability flow for advanced semiconductor nodes and benchmark suite

Topaloglu¹

2014

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Predicting substrate-induced focus error

Cited by 5 publications

References 3 publications

An Effective Chemical Mechanical Polishing Fill Insertion Approach

An Effective Chemical Mechanical Polishing Fill Insertion Approach

Monitoring process-induced focus errors using high-resolution flatness metrology

ICCAD-2014 CAD contest in design for manufacturability flow for advanced semiconductor nodes and benchmark suite

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