2010
DOI: 10.1109/ted.2010.2053864
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Prediction and Modeling of Thin Gate Oxide Breakdown Subject to Arbitrary Transient Stresses

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Cited by 16 publications
(6 citation statements)
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“…Among the various SCR-based ESD protection designs, the diode-triggered SCR (DTSCR) prevails in advanced CMOS technologies due to its design simplicity [3], [4]. When SCR-based protection devices are subject to nanosecond-scale discharges, such as charged device model (CDM) ESD, they are often unable to clamp the pad voltage below the breakdown voltage of thin gate oxides, particularly in sub-100-nm CMOS technologies [5]- [10]. Although the holding voltage of a typical SCR is about 1.5 V, the device cannot be switched instantly from off to on; if the applied ESD pulse has a subnanosecond [11], and it requires that the SCR be augmented by an additional protection element [12], [13].…”
Section: Introductionmentioning
confidence: 99%
“…Among the various SCR-based ESD protection designs, the diode-triggered SCR (DTSCR) prevails in advanced CMOS technologies due to its design simplicity [3], [4]. When SCR-based protection devices are subject to nanosecond-scale discharges, such as charged device model (CDM) ESD, they are often unable to clamp the pad voltage below the breakdown voltage of thin gate oxides, particularly in sub-100-nm CMOS technologies [5]- [10]. Although the holding voltage of a typical SCR is about 1.5 V, the device cannot be switched instantly from off to on; if the applied ESD pulse has a subnanosecond [11], and it requires that the SCR be augmented by an additional protection element [12], [13].…”
Section: Introductionmentioning
confidence: 99%
“…In particular, consideration is given to the fact that gate oxide breakdown voltage is dependent on the rise time and pulsewidth under transient very fast transmission line pulse (VFTLP) stress. For an oxide with a thickness of 13 nm under a VFTLP pulse having 0.2-ns rise time and 5-ns width, the gate oxide breakdown voltage is about 28 V [6]. Fig.…”
Section: High-robustness and Low-capacitance Silicon-controlled Rectimentioning
confidence: 98%
“…The stress impact of VFTLP pulses on the gate oxides is measured by the effective stress voltage, V eff , as the failure metric in the simulation. The V eff is obtained from the gate oxide breakdown (GOB) model derived from an empirical equation known as the Power Law [6]. VFTLP-VT has the same advantages of standard VFTLP, such as well-defined waveforms and adjustable pulse widths/rise times that match the stress pulses in CDM classification testing.…”
Section: Vftlp-vt Testing Configurationmentioning
confidence: 99%
“…V eff corresponds to a DC voltage that, when applied to a gate oxide, yields the same TBD of the oxide as the arbitrary voltage waveform [6]. The GOB model has been implemented in a SPICE-like simulator.…”
Section: Device and Gob Modelsmentioning
confidence: 99%