Process variability-aware transient fault modeling and analysis

Abstract

-Due to reduction in device feature size and supply voltage, the sensitivity of digital systems to transient faults is increasing dramatically. As technology scales further, the increase in transistor integration capacity also leads to the increase in process and environmental variations. Despite these difficulties, it is expected that systems remain reliable while delivering the required performance. Reliability and variability are emerging as new design challenges, thus pointing to the importance of modeling and analysis of transient faults and variation sources for the purpose of guiding the design process. This work presents a symbolic approach to modeling the effect of transient faults in digital circuits in the presence of variability due to process manufacturing. The results show that using a nominal case and not including variability effects, can underestimate the SER by 5% for the 50% yield point and by 10% for the 90% yield point.

Accurate statistical soft error rate (SSER) analysis using a quasi-Monte Carlo framework with quality cell models

“…(3) Compared to t he res ults of Monte Carlo SPICE sim ulation, the proposed QMC framework has error rates of 2.5%, 0.8%, 2.9%, and 2.8%, respectively. Compared to [14] and [11] whe re t he erro r rates are around 10%, our framework is quite accurate, which can be well attri buted to our models.…”

“…Recently, proc ess variations that worsens in sub-90nm technologies have brought a paradigm shift to soft-error research. The authors of [13] first investigate the various sources of process variations, and conclude that the traditional static approach will underestimate circuit SER in presence of process variations [14]. More specifically, according to F igur e 2 from [11], static approaches will underestimate circuit SER by up to 50% under the process variation IJ pr oc = 5% (±3 IJ pr oc covers 99.73% of the distribution), or over 100% under IJ pr oc = 10%.…”

“…More specifically, according to F igur e 2 from [11], static approaches will underestimate circuit SER by up to 50% under the process variation IJ pr oc = 5% (±3 IJ pr oc covers 99.73% of the distribution), or over 100% under IJ pr oc = 10%. However , although [14] and [11], resp ectively, proposes a symbolic-831 Abstract-For CMOS designs in sub 90nm technologies, statistical methods are necessary to accurately estimate circuit SER considering process variations. However, due to the lack of quality statistical models, current statistical SER (SSER) frameworks have not yet achieved satisfactory accuracy.…”

Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA

“…Intermittent faults are primarily caused by the aging of electronic components and crosstalk between wires in integrated circuits. Process variations are the primary cause of transient faults [21]- [23], electromigration (EM) [24], negative bias temperature instability (NBTI) [25], hot carrier injection (HCI) [26], wear out [27], process voltage temperature variations [28], electromagnetic interference (EMI) [29], and electrostatic discharge (ESD) [30]. The intermittent faults' bursty nature causes the system to fail permanently.…”

Statistical Soft Error Rate (SSER) Analysis for Scaled CMOS Designs

“…For design reliability, 15%-40% SER variations are reported in Ramakrishnan et al [2007] under the 70nm technology. Also, Miskov-Zivanov et al [2008] proposed a symbolic approach to propagate transient faults considering process variations.…”