Process variation in embedded memories: failure analysis and variation aware architecture

Agarwal, Amit; Paul, B.C.; Mukhopadhyay, Saibal; Roy, Kaushik

doi:10.1109/jssc.2005.852159

Cited by 133 publications

(74 citation statements)

References 16 publications

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“…Marculescu and Talpes in [23] propose a joint performance, power and variability metric design method considering the statistical uncertainty at microarchitecture level due to gate length and temperature variations. In [2] the authors establish a model describing the failure distribution of on-chip caches under severe process variations. They propose a faulttolerant organization that improves the yield.…”

Section: Discussion and Related Workmentioning

confidence: 99%

Modeling and Characterizing Power Variability in Multicore Architectures

Meng

Huebbers

Joseph

et al. 2007

2007 IEEE International Symposium on Performance Analysis of Systems &Amp; Software

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Section: Discussion and Related Workmentioning

confidence: 99%

Modeling and Characterizing Power Variability in Multicore Architectures

Meng

Huebbers

Joseph

et al. 2007

2007 IEEE International Symposium on Performance Analysis of Systems &Amp; Software

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“…In [5] it is presented a variation-aware cache architecture, which adaptively resizes the cache to avoid accessing to faulty blocks. When a faulty block is accessed, the bitmap information is used to select a non-faulty block in the same row.…”

Section: Related Workmentioning

confidence: 99%

“…In fast Static Random-Access Memory (SRAM) cells, it induces Static Noise Margin (SNM) variability which causes errors [1,2,3] in some cells when working below Vccmin. Different approaches have been devised to deal with this problem [4,5,6]. Most existing proposals provide a fault-coverage (percentage of faults that can be detected/corrected) rather low (see Section 2).…”

Section: Introductionmentioning

confidence: 99%

Enhancing Performance and Energy Consumption of HER Caches by Adding Associativity

Lorente

Valero

Canal

2014

Euro-Par 2013: Parallel Processing Workshops

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Abstract. Unlike other previous techniques, the recently proposed Hard Error Recovery (HER) fault-tolerant cache provides 100% fault-coverage in L1 data caches. This full coverage makes the HER cache appropiate for fault-dominated future technology nodes. An n-way set-associative HER cache implements one cache way with fast SRAM banks and the remaining ways with eDRAM banks to address power and area. Since the number of eDRAM cache blocks used in a specific HER cache organization depends on the cache associativity (i.e., the implemented number of ways), we expect that the performance and energy consumption provided by a given HER cache design strongly depends on the cache geometry. In this work we study the behavior of the HER cache design when applied to a highly associative L1 cache like those found in some modern microprocessors. In particular this work explores a 32KB 8-way associative L1 data cache such as the one used in Intel Haswell microarchitecture. Experimental results show that, at low-power modes compared to a conventional cache with the same storage capacity and number of ways, area, leakage power, and dynamic energy savings of a 4-way HER cache are by 25%, 85%, and 62%, respectively. These percentages are further improved (by 40%, 89%, and 68%, respectively) when the cache associativity is increased to 8 ways, while the performance loss with respect to both an 8-way conventional cache and the 4-way HER cache is minimal.

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“…Reliability issues in both sequential standard-cells and in dedicated SRAM storage cells essentially arise from mismatch between carefully sized transistors due to within-die process variations [21]. In a conventional 6T-SRAM cell, such mismatch manifests itself in three types of failures: a) read failures, b) write failures, and c) hold failures.…”

Section: A Sensitivity Of Scms To Variationsmentioning

confidence: 99%

Benchmarking of Standard-Cell Based Memories in the Sub-$V_{\rm T}$ Domain in 65-nm CMOS Technology

Meinerzhagen

Sherazi

Burg

et al. 2011

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Abstract-In this paper, standard-cell based memories (SCMs) are proposed as an alternative to full-custom sub-V T SRAM macros for ultra-low-power systems requiring small memory blocks. The energy per memory access as well as the maximum achievable throughput in the sub-V T domain of various SCM architectures are evaluated by means of a gate-level sub-V T characterization model, building on data extracted from fully placed, routed, and back-annotated netlists. The reliable operation at the energy-minimum voltage of the various SCM architectures in a 65-nm CMOS technology considering within-die process parameter variations is demonstrated by means of Monte Carlo circuit simulation. Finally, the energy per memory access, the achievable throughput, and the area of the best SCM architecture are compared to recent sub-V T SRAM designs.

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Process variation in embedded memories: failure analysis and variation aware architecture

Cited by 133 publications

References 16 publications

Modeling and Characterizing Power Variability in Multicore Architectures

Modeling and Characterizing Power Variability in Multicore Architectures

Enhancing Performance and Energy Consumption of HER Caches by Adding Associativity

Benchmarking of Standard-Cell Based Memories in the Sub-$V_{\rm T}$ Domain in 65-nm CMOS Technology

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