Programmable Deblocking Filter Architecture for a VC-1 Video Decoder

Citro, R.; Guerrero, María José Abásolo; Lee, Jaebeom; Pantoja, Maria

doi:10.1109/tcsvt.2009.2022699

Cited by 2 publications

(2 citation statements)

References 16 publications

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“…Citro et al [7] proposed a programmable architecture for deblocking filtering. The architecture consists of RISC style Processor Engines (PEs) which control microprogrammable hardware accelerators (HWA) optimized for deblocking filtering.…”

Section: Related Workmentioning

confidence: 99%

Programmable in-loop deblock filter processor for video decoders

Janhunen

Jääskeläinen

Hannuksela

et al. 2014

2014 IEEE Workshop on Signal Processing Systems (SiPS)

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The short time to market cycle and the target to reduce design and verification costs are driving forces to design programmable implementations of the video processing algorithms. We present two processor architectures the first one representing an application-specific instruction set processor (ASIP) design, whereas the second architecture represents a domain-specific instruction-set processor (DSIP) architecture with more general purpose instruction-set. In this work, we present results for H264 and VP8 in-loop deblocking algorithms. The processors are based on the transport triggered architecture which provides scalable instruction-level parallelism and, thanks to its simple structure, lend itself to cost effective designs. Both of the designs are programmed with C language with a minimal additional parallelism markup. The designs fulfill realtime requirements for filtering macroblocks in high-definition video. The first architecture, based on special function units, filters a high-definition stream (1920 × 1080) at 75 fps, whereas the second architecture, which provides a better programmability, filters the stream at 53 fps. The processors run on 200 MHz clock frequency and the areas vary from 146k to 373k gate equivalents depending on the processor architecture.

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Section: Related Workmentioning

confidence: 99%

Programmable in-loop deblock filter processor for video decoders

Janhunen

Jääskeläinen

Hannuksela

et al. 2014

2014 IEEE Workshop on Signal Processing Systems (SiPS)

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“…In the VC-1 deblocking filter design [6], a raster scan order is used as the filter order for reducing the cycle count. The design [7] used a RISC architecture for filtering VC-1. Similar to the design [3], the AVS design [8] used a large separate SRAM with the original filtering order defined by the standard.…”

Section: Introductionmentioning

confidence: 99%

High efficiency data access system architecture for deblocking filter supporting multiple video coding standards

Chien

Jian

Chang

et al. 2012

IEEE Trans. Consumer Electron.

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This paper presents an efficient VLSI architecture of in-loop deblocking filter (ILF) with high efficiency data access system for supporting multiple video coding standards including H.264 BP/MP/HP, SVC, MVC, AVS, and VC-1. Advanced standards, such as H.264 MP/HP, SVC, and MVC, adopt Macro Block Adaptive Frame Field (MBAFF) to enhance coding efficiency which results in the performance bottleneck of deblocking filter due to complex data access requirement. This design challenge has not been discussed in previous works according to our best knowledge. Therefore, we develop a Prediction Data Management (PDM) to manage the input prediction data order of deblocking filter for different coding types (like frame/field) and multiple standards. We also design an extended output frame buffer module to solve the system bus architecture restriction (like 1K boundary and burst length) and achieve high efficiency data access by using MB-based scan order. By using these techniques, we can solve the data accessing design challenge and reduce 67% bus latency. After being implemented by using 90 nm CMOS technology, the proposed work can achieve real-time performance requirement of QFHD (3840×2160@30fps) when operated at 156MHz at the cost of 50.6K gates and 2.4K bytes local memory. The maximum operating frequency of the proposed design, i.e. 370MHz, is higher than the required real-time operating frequency so that voltage scaling may be adopted to reduce power consumption. 1

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Programmable Deblocking Filter Architecture for a VC-1 Video Decoder

Cited by 2 publications

References 16 publications

Programmable in-loop deblock filter processor for video decoders

Programmable in-loop deblock filter processor for video decoders

High efficiency data access system architecture for deblocking filter supporting multiple video coding standards

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