Pseudo-functional testing for small delay defects considering power supply noise effects

Abstract

Detecting small delay defects (SDDs)

Power supply noise control in pseudo functional test

“…In order to strike a balance between over-testing and undertesting, the approach in [2] proposes to test chips under the worst-case functional PSN condition. Delay test considering both functional constraints and power supply noise are reported in [2,18].…”

“…In [17], PSN maximization is modeled as a MIN-ONE problem and a SAT solver is used to maximize the transition count. Two methods [2,3] use justification to maximize transitions on the neighboring cells. While [2] proposes several techniques to speed up the justification process, [3] utilizes a commercial ATPG engine to sensitize neighboring signal lines by virtual test point insertion.…”

“…Two methods [2,3] use justification to maximize transitions on the neighboring cells. While [2] proposes several techniques to speed up the justification process, [3] utilizes a commercial ATPG engine to sensitize neighboring signal lines by virtual test point insertion. Max-Fill [18] computes functional reachable states that induce maximal WSA using both logic simulation and justification.…”

“…In recent years, considerable research effort has been dedicated to at-speed test using the path delay fault model [1][2][3][4] since it has the advantage of capturing the accumulative effects of small delay defects [5]. However, the maximum operating frequency (FMAX) during at-speed scan test may not correlate well to functional and system tests due to the mismatch of power supply noise (PSN) [6,7].…”

Pattern Generation for Understanding Timing Sensitivity to Power Supply Noise

“…These approaches usually consist of two steps -pseudo functional test generation and power supply noise maximization, such as MAX-Fill [3] and PSN-aware PFT [15].…”