Quantitative Analysis of 1D Ultra-Shallow Junctions Using Off-Axis Electron Holography

Abstract

Abstract. The ability to carefully engineer ultra-shallow junctions close to the gate is critical for high performance advanced CMOS devices. Electron holography (EH) has been proposed and investigated as one of the promising techniques for mapping dopant profiles at a nanometer scale in two-dimension (2D). We have developed a low-damage and reproducible sample preparation technique (based on polishing) to prepare samples suitable for EH imaging. Accurate measurements of electro-static potentials across ultra-shallow junctions (both N and P type) by EH have been obtained. Potential profiles derived from ultra-shallow junctions (in the range of 10-30 nm) closely match simulated profiles calculated from secondary ion mass spectroscopy (SIMS) doping profiles of the same junctions. This sets a good baseline for extending the application of electron holography to the quantitative mapping of 2D dopant profiles at close to nanometer spatial resolution.

Electron Holography Characterization of Ultra Shallow Junctions in 30-nm-Gate-Length Metal–Oxide–Semiconductor Field-Effect Transistors

“…This is because the high-energy Ga ion bombardment during FIB thinning (in which the typical acceleration voltage is 30 kV) produces a thick electrically inactive surface layer (dead layer), which degrades electron holography data. 13,14) In addition, Ga ion implantation due to FIB can reportedly change the electronic structure of the specimen surfaces and affect electron holography data. [13][14][15] However, the use of lower ion beam energy reportedly reduces surface damage.…”

“…13,14) In addition, Ga ion implantation due to FIB can reportedly change the electronic structure of the specimen surfaces and affect electron holography data. [13][14][15] However, the use of lower ion beam energy reportedly reduces surface damage. 16) Therefore, we used low-energy Ar-ion milling to reduce the surface damage and to increase the precision of the electron holography experiments.…”

“…For example, high-energy Ga ion bombardment during conventional focused ion beam (FIB) thinning, which is routinely used in preparing TEM specimens from LSI devices, produces a damaged layer on the specimen surfaces and causes thickness corrugations on the specimen. [12][13][14][15][16] These artifacts degrade the experimental hologram and have prevented detailed observations of scaled MOSFETs.…”