Quasi-Resonant Interconnects: A Low Power, Low Latency Design Methodology

Abstract

Abstract-Design and analysis guidelines for quasi-resonant interconnect networks (QRN) are presented in this paper. The methodology focuses on developing an accurate analytic distributed model of the on-chip interconnect and inductor to obtain both low power and low latency. Excellent agreement is shown between the proposed model and SpectraS simulations. The analysis and design of the inductor, insertion point, and driver resistance for minimum power-delay product is described. A case study demonstrates the design of a quasi-resonant interconnect, transmitting a 5 Gb/s data signal along a 5 mm line in a TSMC 0.18-m CMOS technology. As compared to classical repeater insertion, an average reduction of 91.1% and 37.8% is obtained in power consumption and delay, respectively. As compared to optical links, a reduction of 97.1% and 35.6% is observed in power consumption and delay, respectively.

An interconnecting bus power optimization method combining interconnect wire spacing with wire ordering

“…In addition, optimal ordering was proposed by Zuber et al [10] to enhance the effect of power optimal wire spacing. Recently a method of designing quasi-resonant interconnect networks was described by Rosenfeld and Friedman [11] for low power on-chip interconnects.…”