Radiation-Induced Fault Simulation of SOI/SOS CMOS LSI’s Using Universal Rad-SPICE MOSFET Model

Petrosyants, Konstantin O.; Sambursky, Lev M.; Kharitonov, I. A.; Lvov, Boris G.

doi:10.1007/s10836-016-5635-8

Cited by 9 publications

(6 citation statements)

References 20 publications

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“…First, layout-level techniques can be applied as in [2][3][4], such as shallow trench isolation, H-gate, and enclosed annular gate. Through shallow trench isolation, the charge injection node can be isolated from the charge collection node to reduce the possibility of SEU.…”

Section: Single Event Upset (Seu) and Radiation-hardening Design Tech...mentioning

confidence: 99%

Design of Static Random-Access Memory Cell for Fault Tolerant Digital System

Yoon

Park²,

Yoon³

2022

Applied Sciences

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This paper comparatively analyzes the static random-access memory (SRAM) cell designs for fault tolerance. Since SRAM cells are sensitive to radiation-induced single event upsets, various circuit-level approaches have been applied. Compared to the conventional SRAM cell circuits, one possibility is adding redundant storage nodes by means of additional transistors. The strength and weakness of the SRAM cells in terms of various performance aspects—speed, area, power, stability, fault tolerance, etc.—according to the design approaches are compared analytically and discussed. The discussion concludes that, in the future, it is paramount to develop an SRAM cell design with a mitigated trade-off between read/write performance and SEU tolerance.

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Section: Single Event Upset (Seu) and Radiation-hardening Design Tech...mentioning

confidence: 99%

Design of Static Random-Access Memory Cell for Fault Tolerant Digital System

Yoon

Park²,

Yoon³

2022

Applied Sciences

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“…This is mainly caused by trapped charge in the BOX layer [16,17], which can affect the threshold voltage of MOSFETs. Characterization of the radiation resistance (TID effect) of the SOI CMOS technology is given by K. O. Petrosyants in [18] and H. J Barnaby in [19].…”

Section: Soi Cmos Architecturementioning

confidence: 99%

Characterization of pixel sensor designed in 180 nm SOI CMOS technology

et al. 2018

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A new type of X-ray imaging Monolithic Active Pixel Sensor (MAPS), X-CHIP-02, was developed using a 180 nm deep submicron Silicon On Insulator (SOI) CMOS commercial technology. Two pixel matrices were integrated into the prototype chip, which differ by the pixel pitch of 50 μm and 100 μm. The X-CHIP-02 contains several test structures, which are useful for characterization of individual blocks. The sensitive part of the pixel integrated in the handle wafer is one of the key structures designed for testing. The purpose of this structure is to determine the capacitance of the sensitive part (diode in the MAPS pixel). The measured capacitance is 2.9 fF for 50 μm pixel pitch and 4.8 fF for 100 μm pixel pitch at -100 V (default operational voltage). This structure was used to measure the IV characteristics of the sensitive diode. In this work, we report on a circuit designed for precise determination of sensor capacitance and IV characteristics of both pixel types with respect to X-ray irradiation. The motivation for measurement of the sensor capacitance was its importance for the design of front-end amplifier circuits. The design of pixel elements, as well as circuit simulation and laboratory measurement techniques are described. The experimental results are of great importance for further development of MAPS sensors in this technology.

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“…Sarvaghad‐Moghaddam et al 19 and Tang and Li 20 conducted research on the modeling of nanoscale MOSFETs. The modeling of CMOS devices is conducted in Zhang et al, 15 Li et al, 21 and Petrosyants et al 22 Perumal et al 23 present a compact model for flexible analog/RF circuits design with amorphous indium‐gallium‐zinc oxide thin‐film transistors. Petrosyants et al 24 investigated control methods for test environments under high and low temperatures.…”

Section: Introductionmentioning

confidence: 99%

A MOSFET EMC modeling method based on electrical characteristic measurement and simplex optimization and particle swarm optimization

Pan,

Liu,

Ren

et al. 2023

Circuit Theory & Apps

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SummaryMetal oxide semiconductor field effect transistors (MOSFETs) are widely used in various power electronic systems, and the establishment of the electromagnetic compatibility (EMC) model for MOSFETs is crucial for EMC analysis of these systems, especially high‐frequency switching circuits. In this paper, a MOSFET EMC modeling method is proposed based on electrical characteristic measurement, simplex optimization, and particle swarm optimization (PSO), to make MOSFET models meet both functionality and EMC analysis requirements. First, systematic methods for extracting SPICE parameters based on physical MOSFETs are presented, including a proposed curve‐fitting method based on PSO for extracting the CDS‐VDS and ID‐VGS characteristic parameters. Second, parametric influence analyses are conducted on some important model parameters, and the law that these parameters affect the EMC of MOSFETs is obtained. Finally, the preliminary MOSFET model was optimized comprehensively using the simplex method. The measured and simulated results are in good agreement in both time domain and frequency domain. It proves that the established model meets the requirements for model accuracy in terms of both EMC and functionality. Therefore, the proposed EMC modeling method is feasible.

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Radiation-Induced Fault Simulation of SOI/SOS CMOS LSI’s Using Universal Rad-SPICE MOSFET Model

Cited by 9 publications

References 20 publications

Design of Static Random-Access Memory Cell for Fault Tolerant Digital System

Design of Static Random-Access Memory Cell for Fault Tolerant Digital System

Characterization of pixel sensor designed in 180 nm SOI CMOS technology

A MOSFET EMC modeling method based on electrical characteristic measurement and simplex optimization and particle swarm optimization

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