Rapid directed self assembly of lamellar microdomains from a block copolymer containing hybrid

Cheng, Joy Y.; Pitera, Jed W.; Park, Oun-Ho; Flickner, Myron; Ruiz, Ricardo; Black, Charles T.; Kim, Ho-Cheol

doi:10.1063/1.2791003

Cited by 29 publications

(35 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In block copolymer lithography, pseudo hard-mask methods may be developed by use of polymer blocks that have hetero atoms included to provide high etch contrast in e.g. RIE etches [40].…”

Section: Discussionmentioning

confidence: 99%

Plasma etch technologies for the development of ultra-small feature size transistor devices

Borah¹,

Shaw²,

Rasappa³

et al. 2011

J. Phys. D: Appl. Phys.

View full text Add to dashboard Cite

The advances in information and communication technologies have been largely predicated around the increases in computer processor power derived from the constant miniaturization (and consequent higher density) of individual transistors. Transistor design has been largely unchanged for many years and progress has been around scaling of the basic CMOS device. Scaling has been enabled by photolithography improvements (i.e. patterning) and secondary processing such as deposition, implantation, planarization, etc. Perhaps the most important of the secondary processes is the plasma etch methodology whereby the pattern created by lithography is ‘transferred’ to the surface via a selective etch to remove exposed material. However, plasma etch technologies face challenges as scaling continues. Maintaining absolute fidelity in pattern transfer at sub-16 nm dimensions will require advances in plasma technology (plasma sources, chamber design, etc) and chemistry (etch gases, flows, interactions with substrates, etc). In this paper, we illustrate some of these challenges by discussing the formation of ultra-small device structures from the directed self-assembly of block copolymers (BCPs) where nanopatterns are formed from the micro-phase separation of the system. The polymer pattern is transferred by a double etch procedure where one block is selectively removed and the remaining block acts as a resist pattern for silicon pattern transfer. Data are presented which shows that highly regular nanowire patterns of feature size below 20 nm can be created using etch optimization techniques and in this paper we demonstrate generation of crystalline silicon nanowire arrays with feature sizes below 8 nm. BCP techniques are demonstrated to be applicable from these ultra-small feature sizes to 40 nm dimensions. Etch profiles show rounding effects because etch selectivity in these nanoscale resist patterns is limited and the resist thickness rather low. The nanoscale nature of the topography generated also places high demands on developing new etch processes.

show abstract

“…In block copolymer lithography, pseudo hard-mask methods may be developed by use of polymer blocks that have hetero atoms included to provide high etch contrast in e.g. RIE etches [40].…”

Section: Discussionmentioning

confidence: 99%

Plasma etch technologies for the development of ultra-small feature size transistor devices

Borah¹,

Shaw²,

Rasappa³

et al. 2011

J. Phys. D: Appl. Phys.

View full text Add to dashboard Cite

show abstract

“…However, AFM scanning speed is relatively slow, and the spatial resolution is poorer than that of TEM. On the contrary, SEM is currently becoming popular for BCP surface structure analysis, partly owing to a quick imaging process and the ease in specimen preparation [11][12][13][14].…”

Section: Introductionmentioning

confidence: 99%

Phase-selective staining of metal salt for scanning electron microscopy imaging of block copolymer film

Wang

et al. 2010

Ultramicroscopy

View full text Add to dashboard Cite

“…By incorporating inorganic components, these blocks would also conceivably have larger etch contrast. Indeed, recent research on BCP lithography using polystyrene-block-polyethyleneoxide (PS-b-PEO) [95][96][97] shows the possibility of making dense sub-10 nm features, dimensions that are difficult to produce even for electron-beam lithography. Methods such as multi-layer BCPs [47], and inorganic polymer blocks containing polyhedral oligomeric silsesquioxane (POSS) [98] have also clearly demonstrated sub-10 nm feature sizes.…”

Section: Summary and Future Directionsmentioning

confidence: 99%

Block Copolymer Nanostructures for Technology

2010

View full text Add to dashboard Cite

Nanostructures generated from block copolymer self-assembly enable a variety of potential technological applications. In this article we review recent work and the current status of two major emerging applications of block copolymer (BCP) nanostructures: lithography for microelectronics and photovoltaics. We review the progress in BCP lithography in relation to the requirements of the semiconductor technology roadmap. For photovoltaic applications, we review the current status of the quest to generate ideal nanostructures using BCPs and directions for future research.

show abstract

Rapid directed self assembly of lamellar microdomains from a block copolymer containing hybrid

Cited by 29 publications

References 21 publications

Plasma etch technologies for the development of ultra-small feature size transistor devices

Plasma etch technologies for the development of ultra-small feature size transistor devices

Phase-selective staining of metal salt for scanning electron microscopy imaging of block copolymer film

Block Copolymer Nanostructures for Technology

Contact Info

Product

Resources

About