Realistic Projections of Product Fails from NBTI and TDDB

Haggag, A.; Moosa, M.; Liu, N.; Burnett, D.; Abeln, G. C.; Kuffler, M.; Forbes, K.R.; Schani, P.; Shroff, Mehul D.; Hall, M.; Paquette, C.; Anderson, Gary A.; Pan, Danfeng; Cox, Kevin; Higman, J.M.; Mendicino, M.; Venkatesan, S.

doi:10.1109/relphy.2006.251276

Cited by 23 publications

(7 citation statements)

References 3 publications

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“…Here we simultaneously vary the V t of both of the PU and both of the PD devices. We find that degradation of PMOS V t produces increases in the RM V ccmin , while the WM V ccmin decreases, which is consistent with our early finding 12 , and others' results for degradation due to NBTI [5][6][7][8][9] . NMOS V t degradation also leads to increases in the RM voltage and degradation in WM.…”

Section: Modeling Of Sram V Ccmin Driftsupporting

confidence: 92%

Time Dependent Vccmin Degradation of SRAM Fabricated with High-k Gate Dielectrics

Lin

Oates

2007

2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual

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We present the results of simulations of voltage-induced V ccmin drift of SRAMs fabricated with high-k gate dielectrics. We show that high-k based SRAMs are fundamentally more susceptible to V ccmin stability problems because PMOS NBTI and NMOS PBTI lead to an additive degradation in the bit-cell read voltage. Given the differing time dependences of the NBTI and PBTI phenomena, the drift of V ccmin is enhanced at much earlier times compared to SRAMs that have SiO 2 gate dielectric only devices. Maintaining V ccmin stability presents a significantly greater challenge for high-k gate dielectrics compared to SiO 2 .

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Section: Modeling Of Sram V Ccmin Driftsupporting

confidence: 92%

Time Dependent Vccmin Degradation of SRAM Fabricated with High-k Gate Dielectrics

Lin

Oates

2007

2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual

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“…While previous reports have noted the occurrence of V ccmin degradation during stress 1, 2,7,8 , in this paper we show that during high voltage, high temperature stress, SRAM V ccmin exhibits a variety of responses to PMOS NBTI, including V ccmin improvement, as well as degradation. We investigate the root cause of these V ccmin drift phenomena using a novel simulation technique and we show for the first time, the capability to predict the between -die statistical distribution of V ccmin as function of time.…”

Section: Introductioncontrasting

confidence: 45%

Prediction and Control of NBTI -- Induced SRAM V<sub>ccmin</sub> Drift

Lin

Oates

Tseng

et al. 2006

2006 International Electron Devices Meeting

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“…This mechanism may also partially explain why we could not find the PMOS related cell failure. It should be pointed out that cell mismatch induced by degrading the PMOST through NBTI can be problematic to the cache stability [34], [35]. However, similar problem has not been detected in this paper for this technology.…”

Section: Nmos and Pmosmentioning

confidence: 64%

Thin-Gate-Oxide Breakdown and CPU Failure-Rate Estimation

Lee

Mielke

McMahon

et al. 2007

IEEE Trans. Device Mater. Relib.

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Gate-oxide breakdown is a key mechanism limiting IC lifetime. Lifetime is typically extrapolated from accelerated tests on test capacitors, but estimating product reliability from such results requires making a number of often-untested assumptions. This paper details a capacitor-based model and compares the predictions of the model to results from accelerated lifetest of actual logic CPU products, discussing the assumptions which make such a comparison necessary. For the technology studied, lifetest failure rate was somewhat lower than model prediction, and failure analysis indicated that important factors included the different sensitivities of logic circuits versus cache cells and of n and p transistors in the cache. Analysis of the factors involved in determining oxide-breakdown reliability and of the statistical uncertainties in capacitor-based models indicates that it is important to calibrate models to product data, including these effects. Once a model is validated, this paper discusses how it can be used to assess the reliability impact of changes in silicon processing and product use conditions. Index Terms-CPU, failure rate, lifetest, time-dependent dielectric breakdown (TDDB), V CCMIN .

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Realistic Projections of Product Fails from NBTI and TDDB

Cited by 23 publications

References 3 publications

Time Dependent Vccmin Degradation of SRAM Fabricated with High-k Gate Dielectrics

Time Dependent Vccmin Degradation of SRAM Fabricated with High-k Gate Dielectrics

Prediction and Control of NBTI -- Induced SRAM V<sub>ccmin</sub> Drift

Thin-Gate-Oxide Breakdown and CPU Failure-Rate Estimation

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