Reducing cost and ensuring on-time delivery of hybrid-WSI massively parallel computing modules

Abstract

Hybrid-WSI technologies offer an attractive impleinentation route for Massively Parallel Computing (MPC) Modules. However, cost and, especially, delivery problems, still associated with these technologies make MPC manufacturers wary. Uncertainties are mainly caused by limited individual die yields, and loss of good die during the mounting and bonding processes. Although significant research effort is aimed at supplying "known-good-die" and die yields can be expected to improve in the near future, these are likely to be superseded by increased levels of integration. This paper demonstrates how redundancy and reconfiguration can offer a solution to the problem and ensure on-time delivery while reducing the production cost of hybrid-WSI MPC inodules significantly.

Quality-effective repair of multichip module systems

“…where loss represents the decrease rate of b at the n-th cycle in the repair process (for current technology, loss has a value of 70% [4] ) as affecting Y,,,. This equation means that after the n-th repair cycle, the overall yield of the MCM (Yn-l) can be effectively decreased (due to damage) with a finite probability given by 1 -damg,, while the bad parts (1 - Yn-1(1 -damg,)) are repaired with a probability given by XnC(l -loss).…”

“…Repair may degrade the remaining part of the subassembly as reported in [4] (10% to 20% damage in each repair cycle was assumed in [4]). It is assumed that the probability of damage (denoted as damg) due to repair increases, as the MCM undergoes a larger number of repair cycles.…”

“…In [4], an analysis of the repair process of MCMs is presented. It is assumed that repair has higher costs than the original mounting process.…”

“…As the rework of faulty chips may carry the risk of damaging other working chips, the number of repair cycles is usually fixed to two. In this paper, after mounting the chips, the substrate is tested and a non-operational substrate will be subject to a repair and test-cycle [4]. In [4], it is assumed that, due to a finite probability in damaging the originally working chips during repair, each substrate is subject to a full test-cycle after repair.…”