Reduction of Threshold Voltage Hysteresis of MoS₂ Transistors with 3-Aminopropyltriethoxysilane Passivation and Its Application for Improved Synaptic Behavior

Abstract

Although molybdenum disulfide (MoS 2 ) is highlighted as a promising channel material, MoS 2 -based field-effect transistors (FETs) have a large threshold voltage hysteresis (ΔV TH ) from interface traps at their gate interfaces. In this work, the ΔV TH of MoS 2 FETs is significantly reduced by inserting a 3-aminopropyltriethoxysilane (APTES) passivation layer at the MoS 2 /SiO 2 gate interface owing to passivation of the interface traps. The ΔV TH is reduced from 23 to 10.8 V by inserting the 1%-APTES passivation layers because APTES passivation prevents trapping and detrapping of electrons, which are the major source of the ΔV TH . The reduction in the density of interface traps (D it ) is confirmed by the improvement of the subthreshold swing (SS) after inserting the APTES layer. Furthermore, the improvement in the synaptic characteristics of the MoS 2 FET through the APTES passivation is investigated. Both inhibitory and excitatory postsynaptic currents (PSC) are increased by 33% owing to the reduction in the ΔV TH and the n-type doping effect of the APTES layer; moreover, the linearity of PSC characteristics is significantly improved because the reduction in ΔV TH enables the synaptic operation to be over the threshold region, which is linear. The application of the APTES gate passivation technique to MoS 2 FETs is promising for reliable and accurate synaptic applications in neuromorphic computing technology as well as for the next-generation complementary logic applications.

Observation of 2D Conduction in Ultrathin Germanium Arsenide Field-Effect Transistors

“…Differently from few-layer TMD-based transistors, − the transfer characteristic exhibits negligible hysteresis indicating limited charge trapping during a gate voltage loop.…”

Hysteresis Modulation on Van der Waals‐Based Ferroelectric Field‐Effect Transistor by Interfacial Passivation Technique and Its Application in Optic Neural Networks

“…This ΔV th and SS are closely connected to the D it of the gate oxide surface. Therefore, D it was calculated from SS of device using following equation (Equation ( 1)) [41] ( )…”

2D Heterostructures for Ubiquitous Electronics and Optoelectronics: Principles, Opportunities, and Challenges

“…The synaptic devices (refs , , , , − , , , , and − ) are structures that incorporate the functions of electronics and optoelectronics and integrate and inspire with neural cells of humans or animals (Table , ,− Figure a,b, , and Figure a–h ,,,,,, ). The development of artificial cells to replace the broken and damaged ones in the human body is in high demand in healthcare (refs , , − , , , , and ).…”