Relationship between localized wafer shape changes induced by residual stress and overlay errors

Turner, Kevin T.; Veeraraghavan, S.; Sinha, Jaydeep K.

doi:10.1117/1.jmm.11.1.013001

Cited by 21 publications

(24 citation statements)

References 11 publications

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“…We examine the validity of this assumption by using full scale three-dimensional (3-D) FE models, as described in detail elsewhere. 9,10 Wafer shape measurements were made of silicon wafers at two lithography steps in the process flow. The thickness of the 300-mm wafer was assumed to be uniform with a nominal value of 775 μm.…”

Section: Relationship Between Wafer Geometry Andmentioning

confidence: 99%

Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress

Brunner

Menon

Wong

et al. 2013

J. Micro/Nanolith. MEMS MOEMS

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Abstract. Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. Although uniform process-induced stress is easily corrected, nonuniform stress across the wafer is much more problematic, often resulting in noncorrectable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such nonuniform stress-induced wafer distortions. Wafer geometry data can be related to in-plane distortion of the wafer pulled flat by an exposure tool vacuum chuck, which in turn relates to overlay error. This paper will explore the relationship between wafer geometry and overlay error by the use of silicon test wafers with deliberate stress variations, i.e., engineered stress monitor (ESM) wafers. A process will be described that allows the creation of ESM wafers with nonuniform stress and includes many thousands of overlay targets for a detailed characterization of each wafer. Because the spatial character of the stress variation is easily changed, ESM wafers constitute a versatile platform for exploring nonuniform stress. We have fabricated ESM wafers of several different types, e.g., wafers where the center area has much higher stress than the outside area. Wafer geometry is measured with an optical metrology tool. After fabrication of the ESM wafers including alignment marks and first level overlay targets etched into the wafer, we expose a second level resist pattern designed to overlay with the etched targets. After resist patterning, relative overlay error is measured using standard optical methods. An innovative metric from the wafer geometry measurements is able to predict the process-induced overlay error. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.

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Section: Relationship Between Wafer Geometry Andmentioning

confidence: 99%

Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress

Brunner

Menon

Wong

et al. 2013

J. Micro/Nanolith. MEMS MOEMS

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“…This has changed as overlay error budgets have been reduced to the sub-10 nm regime. Several papers examining aspects of process induced overlay errors have been published in the past 5 years (e.g., [2,4,5]). In 2012, our team demonstrated that if a deposited film has a uniform residual stress that does not vary with location on the wafer then the induced distortions can be fully compensated for through the application of standard linear corrections in the scanner [5].…”

Section: Introductionmentioning

confidence: 99%

Monitoring process-induced overlay errors through high-resolution wafer geometry measurements

et al. 2014

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Controlling overlay errors resulting from wafer processing, such as film deposition, is essential for meeting overlay budgets in future generations of devices. Out-of-plane distortions induced on the wafer due to processing are often monitored through high-resolution wafer geometry measurements. While such wafer geometry measurements provide information about the wafer distortion, mechanics models are required to connect such measurements to overlay errors, which result from in-plane distortions. The aim of this paper is to establish fundamental connections between the out-ofplane distortions that are characterized in wafer geometry measurements and the in-plane distortions on the wafer surface that lead to overlay errors. First, an analytical mechanics model is presented to provide insight into the connection between changes in wafer geometry and overlay. The analytical model demonstrates that the local slope of the change in wafer shape induced by the deposition of a residually stressed film is related to the induced overlay for simple geometries. Finite element modeling is then used to consider realistic wafer geometries and assess correlations between the local slope of the wafer shape change induced by the deposition of a stressed film and overlay. As established previously, overlay errors only result when the stresses in the film are non-uniform, thus the finite element study considers wafers with several different nonuniform residual stress distributions. Correlation between overlay and a metric based on a corrected wafer slope map is examined. The results of the modeling and simulations are discussed and compared to recently published experimental results.

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“…If wafers are not chucked completely, overlay and defocus issues may arise in lithography processes. [1][2][3] While wafer chucking is not typically considered a key challenge, recent and future changes to lithography systems and processes have increased the importance of wafer chucking. These changes include: (1) the development of EUV lithography systems that use electrostatic chucks with lower clamping pressures, (2) a move to smaller feature sizes with tighter requirements on defocus and overlay that make complete chucking, down to the nanometer level, critical, and (3) a transition to larger diameter, 450-mm wafers that are thicker and thus stiffer and more difficult to chuck.…”

Section: Introductionmentioning

confidence: 99%

Role of wafer geometry in wafer chucking

Turner

Ramkhalawon

Sinha

2013

J. Micro/Nanolith. MEMS MOEMS

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Abstract. Wafer chucks are used in advanced lithography systems to hold and flatten wafers during exposure. To minimize defocus and overlay errors, it is important that the chuck provide sufficient pressure to completely chuck the wafer and remove flatness variations across a broad range of spatial wavelengths. Analytical and finite element models of the clamping process are presented here to understand the range of wafer geometry features that can be fully chucked with different clamping pressures. The analytical model provides a simple relationship to determine the maximum feature amplitude that can be chucked as a function of spatial wavelength and chucking pressure. Three-dimensional finite element simulations are used to examine the chucking of wafers with various geometries, including cases with simulated and measured shapes. The analytical and finite element results both demonstrate that geometry variations with short spatial wavelengths (e.g., high-frequency wafer shape features) present the greatest challenge to achieving complete chucking. The models and results presented here can be used to provide guidance on wafer geometry and chuck designs for advanced exposure tools.

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Relationship between localized wafer shape changes induced by residual stress and overlay errors

Cited by 21 publications

References 11 publications

Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress

Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress

Monitoring process-induced overlay errors through high-resolution wafer geometry measurements

Role of wafer geometry in wafer chucking

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