Reliability Analysis of Field-Programmable Gate-Array-Based Space Computer Architectures

Abstract

This paper presents an analysis of the radiation tolerance of field-programmable gate-array-based space computers. The primary failure mechanism studied in this paper is single-event effects due to high-energy ionizing radiation. The analysis is performed on the most common architectures deployed on field-programmable gate-arraybased systems including simplex, triple modular redundant, inclusion of spares, and configuration memory scrubbing. The reliability of each system is modeled using a Markov chain to predict its mean time to failure. Orbital dependencies are discussed in addition to a comparison of reliability across different process nodes. Nomenclature L = system lifetime, s p = probability of failure R = reliability T = transition matrix α = rate of context switch, s −1 λ = radiation-induced fault rate, s −1 μ = repair rate, s −1

Reliability Analysis of the SHyLoC CCSDS123 IP Core for Lossless Hyperspectral Image Compression Using COTS FPGAs

“…To solve this problem, low-cost solutions based on implementing RHBD strategies can be applied. Different RHBD techniques have been developed over the years to protect FPGA designs against radiation providing good results [27][28][29].…”

Analytical reliability estimation of SRAM-based FPGA designs against single-bit and multiple-cell upsets

“…Figure 1 shows the #Errors obtained from both the experiments made by fault simulation (Section IV-B) and the estimations made with the proposed model (Eq. (5)(6)(7)(8)(9)(10)(11)(12)). The #Errors of the experiments are shown by dotted blue lines, whereas the estimations are shown by red lines.…”

“…Markov-chain models are one kind of analytical approaches to estimate the reliability of designs running on FPGAs in which the applications are modeled as data flow graphs, representing the dependency of the application modules. For example, the solution proposed by [11] estimates the reliability of FPGA-based designs using Markov-chain models where the SBUs are the object of concern. The solution proposed in [12] splits a design into multiple partitions each of which hardened with Triple Modular Redundancy (TMR) and scrubbing techniques.…”

Co-evolutionary Approach to Reduce Soft Error Rate of Implemented Circuits on SRAM_based FPGA

“…Almost 80% of transistors in an FPGA lay inside this programmable routing network (programmable switches and buffers). In modern FPGAs, more than fourteen layers of metal are used, most of them for routing resources [1].…”