Reliability improvement of 90nm large flip chip low-k die via dicing and assembly process optimization

Chaware, Raghunandan; Hoang, Luu

doi:10.1109/eptc.2006.342785

Cited by 5 publications

(3 citation statements)

References 3 publications

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“…Besides the location of the crack stop, the fracture resistance of the crack stop structure and low-k dielectrics is also important: more resistance means less susceptibility to fracture and larger process margin. In addition, several other techniques have been proposed to improve the mechanical reliability of low-k interconnect including optimization of the dicing process [24] and repair of dicing defects based on chemical reaction [25].…”

Section: B Implementation Of Crack Stop Structurementioning

confidence: 99%

Chip–Package Interaction and Reliability Improvement by Structure Optimization for Ultralow-$k$ Interconnects in Flip-Chip Packages

Zhang

Wang

et al. 2012

IEEE Trans. Device Mater. Relib.

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Mechanical failures in low-k interlayer dielectrics and related interfaces during flip-chip-packaging processes have raised serious reliability concerns. The problem can be traced to interfacial fracture induced by chip-package interaction (CPI). During the packaging processes, thermal stresses arise from the mismatch in coefficient of thermal expansion between the chip and the substrate, which can be directly coupled into the Cu/low-k interconnect structure to drive interfacial delamination. In this paper, finite-element method is used to evaluate the crack driving force induced by CPI and to examine its impact on the reliability of Cu/low-k interconnects for 45-nm technology and beyond. First, the characteristics of CPI are investigated for flip-chip packages using a 3-D multilevel global-to-local modeling method where the crack driving force for the interfacial delamination in Cu/low-k interconnect structures is evaluated. The effects of dielectric and packaging materials are examined for different low-k dielectrics and Pb-based and Pb-free solders. This study is then extended to explore the potential of using structural optimizations to improve the CPI reliability as the technology continues with dimensional scaling and implementation of porous ultralow-k materials.Index Terms-Chip-package interaction (CPI), crack stop, Cu/low-k interconnect reliability, finite-element method, low-k dielectric.

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Section: B Implementation Of Crack Stop Structurementioning

confidence: 99%

Chip–Package Interaction and Reliability Improvement by Structure Optimization for Ultralow-$k$ Interconnects in Flip-Chip Packages

Zhang

Wang

et al. 2012

IEEE Trans. Device Mater. Relib.

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“…the low-k materials are removed in the first step with a laser, then the silicon is cut with a conventional dicing saw in the second step). [32,[37][38][39][40][41][42][43]. Laser dicing greatly reduces the amount of edge chipping.…”

Section: Dicingmentioning

confidence: 99%

Thin silicon wafer processing and strength characterization

Gambino

2013

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

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Thin silicon die (100 um or less) are required for a number of applications, including stacked die packages and three-dimensional integrated circuits (3D-IC). The wafer thinning process is conceptually simple, but requires optimization of the backside finish and dicing to ensure high die strength. High die strength is required to minimize yield loss during assembly and to ensure high reliability during device operation. In this paper, we describe process optimization for thin wafers and thin die, and how these processes affect the fracture strength of silicon.

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“…The adhesion strength between the metal layers in the die is maintained and the stress generated by blade sawing has been minimized. [8] Based on the works and result findings that have been documented to-date, here is our motivation and opportunity to discover and explore more on the process feasibility and robustness of laser grooving in low-k wafer processing.…”

Section: Introductionmentioning

confidence: 99%

Laser grooving characterization for dicing defects reduction and its challenges

Shi¹,

Beng²,

Yow³

2009

2009 11th Electronics Packaging Technology Conference

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Blade sawing has been widely used in semiconductor industry and it is the most conventional process in semiconductor manufacturing to produce singulated ICs. This well established dicing technique poses challenges to process next generation of wafer when the wafer fabrication technology is fast scaling down in node size to 90-, 45-, 32and 22-nm where low-k dielectric is used. ILD (Inter-Layer Dielectric) and metal layers peelings, cracks, chipping, and delamination are the most common dicing defects observed on low-k wafer processed by the traditional blade sawing techniques. This paper presents an experimental study to improve the dicing performance and quality on processing low-k wafer by using a combination of laser grooving process and traditional blade sawing technique. Some low-k wafers were used as test vehicles. The laser process outcomes and responses are governed by the changes of process input parameters such as laser power, repetition rate, grooving feed speed, defocus amount and street index. The effects of the process parameters on the laser kerf geometry, grooving edge quality and defects are evaluated by using optical microscopy and scanning electron microscopy (SEM). Experimental results have shown that the dicing quality produced by using a combination of laser grooving and blade sawing technique can significantly minimize the dicing defects. It is one of the potential solutions to address the quality and yield issues in low-k wafer dicing. The key challenges of laser grooving and recommended future development works are discussed.

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Reliability improvement of 90nm large flip chip low-k die via dicing and assembly process optimization

Cited by 5 publications

References 3 publications

Chip–Package Interaction and Reliability Improvement by Structure Optimization for Ultralow-$k$ Interconnects in Flip-Chip Packages

Chip–Package Interaction and Reliability Improvement by Structure Optimization for Ultralow-$k$ Interconnects in Flip-Chip Packages

Thin silicon wafer processing and strength characterization

Laser grooving characterization for dicing defects reduction and its challenges

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