Resistive RAM With Multiple Bits Per Cell: Array-Level Demonstration of 3 Bits Per Cell

Le, Binh; Grossi, Alessandro; Vianello, E.; Wu, Tung-Yu; Lama, Giusy; Beigné, Edith; Wong, H.-S. Philip; Mitra, Subhasish

doi:10.1109/ted.2018.2879788

Cited by 49 publications

(39 citation statements)

References 7 publications

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“…Further, our sensor scales well from 2-bit to 3-bit MLC by requiring only one additional flip-flop and logic gate (for 3-bit counter). The serial approach will require 7 I REF [20], while the parallel approach will require 7 op-amps and resistors [19] to sense 3-bits/cell.…”

Section: Significance Of Resultsmentioning

confidence: 99%

A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM

Reuben

Fey

2019

2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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The quest to increase memory density in Resistive Random Access Memory (RRAM) has motivated researchers to store more bits/cell by implementing Multi-Level Cell (MLC) or multi-bit RRAM. Implementing multiple states narrows the distance between states, making sensing of MLC RRAM a challenging task. In this paper, we present a circuit which senses the state of a MLC by converting the current drawn from the cell to voltage pulses, where the number of pulses is proportional to the current's magnitude. The circuit distinguishes between the states by the relative current's magnitude and hence does not require an absolute reference. Simulations in IHP's 130 nm CMOS technology confirmed fast (single step) sensing while tolerating appropriate variations in the sensed resistance. The proposed circuit is also area efficient when compared to conventional parallel sensing approach.

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Section: Significance Of Resultsmentioning

confidence: 99%

A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM

Reuben

Fey

2019

2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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“…To further enhance the memory density and speed, investigation towards next-generation memory technology with new computing principles is needed to satisfy the ever-growing appetite for data and information [81]. To this end for on-chip weight storage and artificial synapses, emerging NVM (eNVM) devices including the memristors (resistive random-access memories), phase change memories, magnetoresistive random-access memory or spintronic devices and ferroelectric transistor-based RAM (Fe-RAM) have been anticipated and demonstrated (shown in figure 7) [17,73,75,79,[82][83][84][85][86][87][88][89].…”

Section: Distributed Memory and Computingmentioning

confidence: 99%

“…In order to perform data storage and computation over large areas, such as in eSkin, a single memristor is not going to solve the problem. Owing to the excellent scalability and easy stack (three-dimensional (3D)) integration, the cross-bar array of memristors has been studied as a promising architecture for high storage density consuming low power [86,[114][115][116]. However, with the cross-bar architecture, the passive memristor device encounters challenges such as cell-to-cell interference.…”

Section: (A) Memristors: Memory and Computing Togethermentioning

confidence: 99%

“…However, with the cross-bar architecture, the passive memristor device encounters challenges such as cell-to-cell interference. This is owing to the parasitic leakage/sneak path which leads to current leakage through the interconnected low resistance state (unselected) cells and induces unnecessary power consumption and an improper read out [86,[114][115][116].…”

Section: (A) Memristors: Memory and Computing Togethermentioning

confidence: 99%

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Soft eSkin: distributed touch sensing with harmonized energy and computing

Soni

Dahiya

2019

Phil. Trans. R. Soc. A.

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Inspired by biology, significant advances have been made in the field of electronic skin (eSkin) or tactile skin. Many of these advances have come through mimicking the morphology of human skin and by distributing few touch sensors in an area. However, the complexity of human skin goes beyond mimicking few morphological features or using few sensors. For example, embedded computing (e.g. processing of tactile data at the point of contact) is centric to the human skin as some neuroscience studies show. Likewise, distributed cell or molecular energy is a key feature of human skin. The eSkin with such features, along with distributed and embedded sensors/electronics on soft substrates, is an interesting topic to explore. These features also make eSkin significantly different from conventional computing. For example, unlike conventional centralized computing enabled by miniaturized chips, the eSkin could be seen as a flexible and wearable large area computer with distributed sensors and harmonized energy. This paper discusses these advanced features in eSkin, particularly the distributed sensing harmoniously integrated with energy harvesters, storage devices and distributed computing to read and locally process the tactile sensory data. Rapid advances in neuromorphic hardware, flexible energy generation, energy-conscious electronics, flexible and printed electronics are also discussed. This article is part of the theme issue ‘Harmonizing energy-autonomous computing and intelligence’.

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“…That reduction paved the way for the introduction of the multi-bits per cell paradigm that is usually achieved by tailoring the CF properties through multi-level programming algorithms [18]- [24]. Table 1 summarizes the most common approaches found in the literature.…”

Section: Introductionmentioning

confidence: 99%

Toward Reliable Multi-Level Operation in RRAM Arrays: Improving Post-Algorithm Stability and Assessing Endurance/Data Retention

Pérez

Zambelli

Mahadevaiah

et al. 2019

IEEE J. Electron Devices Soc.

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Achieving a reliable multi-level operation in resistive random access memory (RRAM) arrays is currently a challenging task due to several threats like the post-algorithm instability occurring after the levels placement, the limited endurance, and the poor data retention capabilities at high temperature. In this paper, we introduced a multi-level variation of the state-of-the-art incremental step pulse with verify algorithm (M-ISPVA) to improve the stability of the low resistive state levels. This algorithm introduces for the first time the proper combination of current compliance control and program/verify paradigms. The validation of the algorithm for forming and set operations has been performed on 4-kbit RRAM arrays. In addition, we assessed the endurance and the high temperature multi-level retention capabilities after the algorithm application proving a 1 k switching cycles stability and a ten years retention target with temperatures below 100 • C.

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Resistive RAM With Multiple Bits Per Cell: Array-Level Demonstration of 3 Bits Per Cell

Cited by 49 publications

References 7 publications

A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM

A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM

Soft eSkin: distributed touch sensing with harmonized energy and computing

Toward Reliable Multi-Level Operation in RRAM Arrays: Improving Post-Algorithm Stability and Assessing Endurance/Data Retention

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