Resource-Shared Crypto-Coprocessor of AES Enc/Dec With SHA-3

Abstract

Cryptographic co-processors are integral to the modern System-on-Chips. Flexibility in such designs serves dual purpose, i.e., it enables acceleration of different essential cryptographic primitives (Encryption/Authentication/Pseudo Random Number Generation (PRNG) ) and also results in design compaction via resource sharing. In this context, a novel resource-shared crypto-coprocessor, named AE$HA-3 is presented, which combines two National Institute of Standards and Technology (NIST) standardized algorithms, i.e., Advance Encryption Standard (AES) and Secure Hash Algorithm-3 (SHA-3). Due to algorithmic dissimilarities, so far no resource-shared implementation enabling AES key scheduling/ enc/dec and SHA-3 has been presented. AE$HA-3 exploits resource-sharing for area reduction, i.e., integration of Look-Up-Tables (I-Tables) for AES enc/dec; logical optimization of Six Input Equation (SixIE) for SHA-3; a Unified XOR Section to carry out both key whitening in AES and SHA-3 transformations. Furthermore, the AES key scheduling was performed using the same resource-shared hardware. The proposed AE$HA-3 on Xilinx Virtex FPGA family results in highest hardware efficiency in terms of Throughput per Slice (TPS), along with a 49.37% area consumption reduction, when compared against the smallest stand-alone implementations presented to date.

AES Sbox Acceleration Schemes for Low-Cost SoCs

“…Table II summarizes a performance comparison with other works at the minimum energy point. Although the energy efficiency is similar to the one reported in [7] and [6], authors in [7] employed non-standard logic cells, and authors in [6] implemented an additional memory macro inside the DTLS processor. In contrast, this work demonstrates an approach that fits in more general-purpose systems and low-cost technology nodes, enabling complex security instances in multiple embedded applications.…”

“…Addressing AES acceleration requires special attention for the substitution byte operation (Sbox) resourcehungry block inside the AES algorithm [5]. Although some AES implementations report high energy-efficiency values [6], [7], they rely on adding exclusive-use memory macros and non-standard logic cells.…”

On-the-Fly Parallel Processing IP-Core for Image Blur Detection, Compression, and Chaotic Encryption Based on FPGA

“…Moreover, the proposed system has the highest throughput, which is even twice as fast as a simple DCT compression and stream cipher system [47]. Also, the throughput of the proposed system is 62% higher than the FPGA-based system presented in [62], which accommodates a single AES-128 core with Keccakf[400]. Regarding the HW implementation area, the proposed system has the largest slice utilization.…”

VLSI Architecture of S-Box With High Area Efficiency Based on Composite Field Arithmetic

“…In [21], a compact AES through optimizing the mix columns and inverse mix columns transformations was obtained. The work [22] shared the circuitry of AES and SHA-3. A 60 Gbps reconfigurable cryptographic processor, including AES and SHA algorithms, was proposed in [23].…”