Review of the Nanoscale FinFET Device for the Applications in Nano-regime

Abstract

Background: The insatiable need for low-power and high-performance integrated circuit (IC) results in the development of alternative options for metal oxide semiconductor field effect transistor (MOSFET) in the ultra-nanoscale regime. The practical challenge of the device scaling limits the use of MOSFET for future technology nodes. ICs are equipped with billions of transistors whose size must be scaled while increasing performance. As the size of the transistor shrinks for the new technology node, the control of the gate over the channel also reduces, leading to sub-threshold leakage. The non-planar technology is the potential methodology to design the ICs for the future technology nodes. The fin-shaped field effect transistor (FinFET) is the most valuable non-planar technology. High sub-threshold slope, better short channel effect (SCE) control, high current drive strength, low dopant-prompted variations, and decreased power dissipation are the prominent features of FinFET technology. Objective: FinFET is an advanced version of MOSFET in terms of geometrical structure. Therefore, in this review paper, the different geometrical structures, working operations, design challenges, future aspects, and the different configurations of FinFETs are presented. The performance of the different configurations of a 1-bit full adder is evaluated and compared. Methods: An overview of FinFET evolution from the planar MOSFET, along with its architecture supported by the requisite equations, is presented in the paper. Besides this, it also gives an insight into the circuit simulation using the FinFETs for the process voltage temperature (PVT) variations, width quantization, design challenges, and the future of FinFETs. A comparative study of FinFET-based 1-bit full adder using various techniques is done to compute and compare the leakage power, delay, and power delay product (PDP). Results: The full adders using FinFETs show less leakage power and PDP. The AND-OR logic-based hybrid full adder using FinFETs shows the least energy consumption per switching. FinFET-based gate diffusion input adder shows a 74 % reduction in dynamic power compared to the full adder using MOSFET technology. The low power FinFET-based full adder shows a 54.16 % reduction in leakage power compared to the MOSFET-based full adder. The results signify the effect of multi-gates in curbing the leakage power dissipation. Conclusion: MOSFET faces the practical challenge of device scaling and SCEs at lower technology nodes. It initiates the multi-gate technology for future system generation. FinFET has the capability to design low-power and high-performance circuits in an ultra-nanoscale regime. The geometrical structure of FinFET plays a key role to improve the performance metrics in an ultra-nanoscale regime.

Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology

“…The need for continuous scaling in MOS devices owing to various short channel effects [29][30][31][32] forced the designers to look for alternative to both the MOS technology and the binary logic. MVL was proposed as a substitute for binary logic to cope with the enormous area and power consumption associated with the interconnects in binary logic design [33,34].…”

Design analysis of a low-power, high-speed 8 T SRAM cell using dual-threshold CNTFETs

“…where a 0 is the carbon-carbon bonding length. Equation (3) gives the relation between the V th and D CNT [21].…”

“…As electronic devices and the power supply voltage have continued to scale, the challenge of creating a lowpower and high-speed memory solution has become increasingly complex. At the 32-nm node, the very largescale integration (VLSI) designers are facing significant challenges, including an increase in leakage current, mobility degradation, and threshold voltage (V th ) variation [2,3]. Historically, the subthreshold swing in current in complementary metal-oxide-semiconductor (CMOS) devices has not been able to be scaled below 60 mV/ decade [4].…”

Analytical analysis and linearity performance of dual metalhigh‐KSchottky nanowireFET(DM‐HK‐SNWFET)

“…FinFET technology, despite its advancements, has drawbacks including complex and costly manufacturing, higher leakage currents, increased power consumption, performance variations due to fin width variability, and reliability issues. These limitations emphasize the importance of ongoing research to overcome FinFET challenges 3–5 . The Gate‐all‐around nanosheet field‐effect transistor (FET) is an innovative electronic device that has recently gained significant attention.…”

“…These limitations emphasize the importance of ongoing research to overcome FinFET challenges. [3][4][5] The Gate-all-around nanosheet field-effect transistor (FET) is an innovative electronic device that has recently gained significant attention. Gate-all-around nanosheet FET is an advanced transistor design that provides exceptional electrostatic control and performance.…”