RF modeling of 40‐nm SOI triple‐gate FinFET

Abstract

These last years, the triple-gate fin field-effect transistor (FinFET) has appeared as attractive candidate to pursue the complementary metal-oxide semiconductor technology roadmap for digital and analog applications. However, the development of analog applications requires models that properly describe the static and RF behaviors as well as the extrinsic parameters related to the three-dimensional FinFET architecture, in order to establish adequate design strategies. We demonstrate the feasibility of the compact model developed for symmetric doped double-gate metal-oxide-semiconductor field-effect transistor (symmetric doped double-gate MOSFET) to reproduce the experimental dc and RF behaviors for 40-nm technology node Silicon-on-Insulator triple-gate FinFETs. Extrinsic gate capacitances and access extrinsic resistances have been included in order to properly predict the transistor small-signal behavior, the current gain, and the maximum available power gain cut-off frequencies. Finally, the improvement of the FinFET RF characteristics by the reduction of the parasitics is addressed. Figure 13. Comparison between the modeled (lines) and experimentally obtained (dots) maximum oscillation frequency. Figure 14. Simulated maximum oscillation frequency vs. source/drain fin extension for several values of fin spacing. 476 A. G. MARTINEZ-LOPEZ ET AL.

A broadband small‐signal model extraction methodology over 0.2‐220 GHz for bulk FinFETs in RF CMOS technology

“…Finally, we focus on extraction of the small‐signal equivalent circuit. Many studies have proposed accurate modeling procedures for extracting equivalent circuits of microwave transistors . On the basis of these studies, we propose an innovative model extraction method and verify this method with measured data.…”

“…5 Therefore, most efforts in the literature have aimed to develop accurate and reliable models to support circuit design and to provide feedback for the fabrication process. Small-signal models that can be used for FinFET modeling have been extensively reported [4][5][6][7][8][9][10][11][12][13][14][15] but were either mainly verified below 110 GHz or verified primarily by data obtained by a 3-D simulator. 4,6,7 In 2017, Wu et al proposed a 220-GHz compact equivalent circuit model (ECM) 12 ; in 2015, Katayama et al proposed the successful modeling of common-source metal-oxide-semiconductor field-effect transistor (MOSFET) fabricated in a 65-nm low-power (LP) CMOS process up to 330 GHz.…”

Numerical modeling of process parameters on RF metrics in FinFETs, junctionless, and gate‐all‐around devices

“…Because these devices use ultrathin bodies as their channel, undoped channels can be used as one of the solutions to suppress short channel effects. Abundant literature was available on conventional DG FinFETs and its Radio Frequency (RF) performance . At the present moment, sensitivity analysis of RF performance is only sparsely considered in the literature.…”

“…Abundant literature was available on conventional DG FinFETs and its Radio Frequency (RF) performance. [1][2][3][4][5][6][7] At the present moment, sensitivity analysis of RF performance is only sparsely considered in the literature. To address this issue, a detailed and systematic sensitivity analysis is carried out in this study.…”

A 1D numerical model for rapid stress analysis in bipolar junction transistors

“…Numerical modeling is used as a powerful tool to solve challenging engineering problems in semiconductor devices [18][19][20], and various new approaches are investigated to speed up the numerical process as high accuracy within a reasonable run time is highly desired [21]. In the case of mechanical stress analysis, numerical modeling and simulation avoid a multitude of practical challenges associated with fabrication, complex lithographic and material growth processes and application of controlled stress in different orientations for measurement.…”