Robust wiring networks for DfY considering timing constraints

Panitz, P.; Olbrich, Markus; Barke, Erich; Koehl, J.

doi:10.1145/1228784.1228800

Cited by 10 publications

(10 citation statements)

References 12 publications

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“…Redundancy with respect to opens is offered and functional yield is increased. Lately, this has been exploited in several publications [3,5,6]. The authors of [5] propose local loops to increase the redundant via rate.…”

Section: Non-tree Routingmentioning

confidence: 99%

“…Local loops have a restricted size and can therefore be neglected with respect to timing analysis. Whereas local loops only mask via opens, non-tree topologies as described in [3,6] mask both via and wire opens. It is to be noted that a significant fraction of opens are wire opens [4] that cannot be masked by redundant via insertion.…”

Section: Non-tree Routingmentioning

confidence: 99%

“…Non-tree routing, which is known for decades, has become more and more popular lately [3,5,6,8]. Loops provide redundant signal paths to the sinks and mask open defects.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Considering possible opens in non-tree topology wire delay calculation

Panitz

Olbrich

Barke

et al. 2008

Proceedings of the 18th ACM Great Lakes Symposium on VLSI

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Non-tree routing experiences an increasing interest as technology scales into the nanometer range. Via and wire opens have become the main yield detractors considering random spot defects due to the additive manufacturing process of copper wires. Wiring networks containing loops offer some robustness against open defects which increases functional yield. State-of-the-art delay calculation enables the treatment of loops but does not provide an adequate solution for timing analysis in the presence of an open. If the delay in the presence of an open is not properly analyzed, a functional fail will be masked and replaced by a parametric fail which is only detectable applying delay testing. In this paper we present a new method to rapidly calculate the maximum delay if an open occurs in the net. For topologies consisting of non-adjacent loops we provide proof that the worst delay considering the Elmore delay metric can be found in 2N + 1 delay calculations, whereas N is the number of loops in the net.

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Section: Non-tree Routingmentioning

confidence: 99%

Section: Non-tree Routingmentioning

confidence: 99%

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Considering possible opens in non-tree topology wire delay calculation

Panitz

Olbrich

Barke

et al. 2008

Proceedings of the 18th ACM Great Lakes Symposium on VLSI

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“…Post-processing may include wire spreading within or across layers [2], via duplication [2,9], shifting [19] and widening [22], improvement of via metal overlap, wire and jog widening [1], and more [3,22]. Although many authors point out that, due to the switch from aluminum to copper metallization, opens today dominate over shorts failures [6,12], and wire widening is still mainly discussed only as a measure to improve electromigration [4,8] or timing [18] (with [1] as an early exception). SFF improves routing yield by concurrent wire spreading and fattening within one layer, with the following main distinctive features:…”

Section: Introductionmentioning

confidence: 99%

Concurrent wire spreading, widening, and filling

Rizzo¹,

Melzner

2007

Proceedings of the 44th Annual Conference on Design Automation - DAC '07

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Automated design tools produce layouts complying with all design rules (DRs). However, most wires are designed with minimum width, making them susceptible to random defect induced interruptions (opens). Spaces between wires are also often designed at minimum size, causing yield loss from random defect induced connections (shorts). SFF ("Spread -FattenFill") is a methodology to improve layout -specifically for routing metal layers -in terms of yield loss related to opens and shorts. Additionally, a novel fill concept improves metal density uniformity. In this paper, we will explain issues that were observed and addressed in the implementation on a real layout, and present results achieved in the first experiment on silicon.

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“…Starting with a MRST and a given WL budget the algorithm adds augmenting paths to the tree that greedily maximize the WL that is protected by loops divided by the WL increase. In [5] we show that this greedy approach can be enhanced by removing edges shared by multiple loops to reach a better robustness versus additional wire length trade-off.The fan-out of repeater networks is often above 100 terminals. Therefore, a topology solution close to a MRHC is preferred.…”

mentioning

confidence: 99%

Design of robust signal and clock networks

Panitz

Olbrich

Barke

et al. 2007

Proc Appl Math and Mech

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As technology scales down into the nanometer region new design challenges emerge. Wire delays become the performance bottleneck in VLSI circuits. Copper is introduced as new wiring material because of its low sheet resistivity, hence low signal propagation delay. The main defect mechanism shifts from shorts to opens due to the different manufacturing process for copper wires. Open defects limit functional yield. Parametric yield decreases because of timing uncertainties emerging from manufacturing variation. Clock skew variation becomes critical because it may shorten the cycle length of the critical path. The variation of signal nets has to be considered simultaneously avoiding overly pessimistic designs. Design techniques which reduce the variation of design parameters avoid over design and increase parametric yield.Whereas tree topologies have been applied due to their minimal wire length, the application of generic routing graphs provides multiple paths to specific sinks. Multiple paths from source to sink increase the robustness against open defects and smoothes the effect of variation. New design techniques applying loops in VLSI wiring networks are the topic of this abstract.Millions of signal communication networks have to be designed on an integrated circuit (IC). Those networks can be classified according to their application. Signal nets connect a driving cell to a plurality of receiving cells. The ports of the cells are referred to as terminals and their physical representations are called pin. If the load of the driving cell is beyond its driving capabilities due to the large fan-out or wire length of the net, repeaters will be inserted and a repeater network is created. A repeater network consists of different nets that propagate the same signal or its inverse. A clock signal synchronizes the whole design. It is distributed via the clock network to all synchronous storage elements in a clock domain.There are four major trends that drive the development of IC circuit design in general and especially the design of onchip communication networks. With the integration of more and more devices per unit area and the demand for higher clock frequencies it is important to minimize the power dissipation and wire congestion on the chip. Additionally, the clock frequency is a constraint and yield is a maximization objective. A decade ago these objectives were adressed by applying routing trees as net topologies. With decreasing feature sizes trees have to be reconsidered because other topologies offer advantages. Topologies containing loops offer some robustness against opens. Additionally, an averaging effect can be exploited if the signal is propagated via multiple signal paths. If the signal arrives early on the fast path and late on the slow path, the arrival time of the signal is averaged. Therefore, loop topologies help to increase functional and parametric yield.The main advantage of trees is their minimal wire length (WL). Topologies containing loops always have an increased WL compared to trees. Extre...

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Robust wiring networks for DfY considering timing constraints

Cited by 10 publications

References 12 publications

Considering possible opens in non-tree topology wire delay calculation

Considering possible opens in non-tree topology wire delay calculation

Concurrent wire spreading, widening, and filling

Design of robust signal and clock networks

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