ROS: an extremely high density mask ROM technology based on vertical transistor cells

Abstract

IntroductionFor the replacement of conventional mass storage systems by semiconductor memory technologies very high density memories are demanded. A novel non-volatile semiconductor-memory technology called Record on Silicon (ROS) incorporating a vertical cell is aiming at this objective. Based on a cell size of about 3F2 (F denotes the minimum feature size), the technology is enabling an approximately twofold packing density compared to conventional, planar ROM and pushes into market segments for non-semiconductor memories in the multimedia arena. Relying on a 256M-DRAM technology, a 1 G ROMdevice is already within the reach of this technology The new type solid state memory chip is designed for use in notebooks, mobile phones, portable music players and in-car information systems, personal digital assistants and notebook computers.The key of the new technology is a cell concept based on a vertical MOS transistor in a trench which allow to use the bottom of the trench as additional, selfaligned tiitline and thus to double the bitline density. In the following, the new process, furtheron denoted as ROS-process, is described. First the process sequence is outlined, then the characteristic data of the key devices are given and finally the features of the ROS-technology are demonstrated by means of a 1 Mbit-ROM. Memory cell conceptIn order to issue a memory cell of half the size of a regular cross point cell, adjacent bitlines are not isolated from each other by a planar, Fsized spacing but by a vertical spacing, formed by the trench sidewall The bitlines on the surface and on the bottom of the trenches are selfaligned, the pitch of the bitlines can be halved. Consequently, the memory MOS-devices located in a NOR-configuration in between the bitlines are to be formed at the sidewalls of the trenches (Fig.la\ The area requirement of this memory cell is defined by the projection of this 3-D-configuration onto the wafer surface. Due to overlay tolerances and pattern transfer accuracies, the cell size amounts to about 3Fz which value has, to be compared to the approximately 5-6 Fz of the planar mask ROM cell. TechnologyFor test purposes, the vertical cell concept was integrated into the process pattern of a 0.!5 vm CMOS process used for the logic periphery of the ROM according to the process flow of Fig.2. Since the Vth of the vertical transistor has to be adjusted by the bulk dopant level [2], the process was started by p-well formation for the memory array, followed by CMOlS twin well formation and poly buffered LOCOS-oxidation. Afterwards the surface-bound diffused bitline was formed. Trenches were then opened and the trench-bottom bound bitlines were formed. Trench filling by a deposition / etchback process completed this module. 14 program etch step defined openings for vertical transistor formation at sites, were a "0" was intended to be stored The gateoxide was grown simultaneously for the CMOSperiphery and the vertical transistors. In order to prevent any segregation driven depletion of the p-well dopant concent...

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