Routability-driven placement algorithm for analog integrated circuits

Abstract

To obtain good layout quality and reliability, placement is a very important stage during the physical design of analog circuits. Many works have been proposed to consider topological constraints for analog placement, and they devote to generate compact placements to minimize area and wirelength. However, a compact placement may induce unwanted routing issues. In order to reduce parasitics and cross-talk effects during the routing phase, wires are preferred not to pass above the active area of analog devices. Therefore, it is required to preserve enough routing spaces between devices for successful routing. Currently, there exists limited works studying routability for analog placement, but none of these works consider that symmetry property must be maintained during placement expansion. In this paper, we present a two-stage routability-driven analog placer based on ASF-B*-tree and HB*-tree representations. To reduce running time, our placement algorithm first generates a compact placement to minimize wirelength and area without considering congestion problem. Then, routing congestion regions are expanded locally to resolve the routability problem. Most importantly, the symmetry property of analog placement is always satisfied during the expansion process. Experimental results show that our analog placer can effectively minimize routing congestion without violating the symmetry property after placement expansion.

Simultaneous analog placement and routing with current flow and current density considerations

“…The left and right space nodes correspond to the right and top space besides the module (Figure 4(b)), respectively. Different from the previous work [12], our space node employs linking-control points to provide a substantial basis for resource reservation and allocation, which can effectively reflect the required routing resource to route the interconnects with variable wire widths and current directions, and guide the enhanced B*-tree to a better layout result.…”

“…The later work [8] proposed a sequence-pair representation with a shaped-based formulation to simultaneously express modules and interconnects. Recently, Prieto et al and Lin et al worked on two-stage frameworks to consider the layout routability at the placement stage earlier [20,12]. However, the incremental reshaping and moving may not be able to handle the multiple terminal nets, and also require some post-optimizations to further improve the routing quality.…”

Laser

“…Previous works did not consider the required routing resource in the placement stage [8][9][10] or used an unfaithful congestion to adjust the generated placement [12][13][14]. To accurately predict the required routing resource during placement and generate nonstochastic placements, a routability-aware analog placement flow is proposed.…”

“…In the literature, layout automation techniques for analog circuits are also a popular research direction [8][9][10][11][12][13][14]. In recent years, many researches [8][9][10] focus on studying the analog placement problem to consider the extra layout constraints such as matching, proximity, etc.…”

“…Previous works [8][9][10] do not consider the routing resource in the placement stage and will incur compact placements which are not practical in analog designs. Previous works [12][13][14] perform congestion-driven adjustments during placement. However, the estimated routing congestion may not faithfully represent the required routing resource.…”