Scalable modeling of Through Silicon Vias up to milimeter-wave frequency

Primary approach of 3DIC packaging usually adopts organic substrates or silicon interposer as the intermedium between multi-integrated circuits (ICs) and printed circuit board. Current organic substrates face the limitations in poor dimensional stability, trace density and CTE mismatch to silicon. Silicon interposer is a good solution for high-pin-count ICs and high performance applications based on the mature Si technology of advance via formation and fine line Cu damascene multilevel interconnection process, but silicon interposer is limited by high cost. Glass is proposed as ideal interposer material due to high resistivity, low dielectric constant, low insertion loss and adjustable coefficient of thermal expansion (CTE) for the 3DIC assembly integration and most importantly low cost solution, [1-4]. The main focus of this paper is on (a) TGV electrical design, simulation and characterization, (b) wafer level integration in TGV formation, two RDL on the front-side, one RDL on the backside and polymer-based PBO for the passivation, (c) assembly process of silicon chip stack on the glass interposer with Kelvin resistance measurement. The glass interposer was assessed to have excellent electrical characteristicsand is potentially to be applied for 3D product applications.

show abstract

“…According to Kuan-Chung Lu's [7] measurement, the insertion loss of TSV was 1.0 ~ 1.5 dB at 10GHz. In Fig.…”

Section: Scattering Parameters ( S Parameters )mentioning

confidence: 99%

Performance and process characteristic of glass interposer with through-glass-via(TGV)

Chien

Lee

et al. 2013

2013 IEEE International 3D Systems Integration Conference (3DIC)

View full text Add to dashboard Cite

show abstract

Wideband and scalable equivalent-circuit model for differential through silicon vias with measurement verification

Horng

2013

2013 IEEE 63rd Electronic Components and Technology Conference

Self Cite

View full text Add to dashboard Cite

The three-dimensional integrated circuit has attracted much attention because of evolving functions in today's integrated circuit products and continuing demands for low power consumption and miniature chip size. Through silicon vias (TSVs) provide a vertical interconnection between stacked dies with much shorter and denser connectivity than the hybrid horizontal and bondwire interconnects in conventional use. Moreover, a differential interconnect is more commonly used in high-speed digital circuits for its higher immunity to common-mode noise than a single-ended one. Therefore, a scalable physical model for differential TSVs has been proposed in this work. Consequently, the mixed-mode S-parameters were generated from the established model to compare electrical performance between a GSSG-and GSGSG-type differential TSV. Additionally, with the help of a double-sided probing system, four-port Sparameters were measured up to 40 GHz to validate the modeled results.

show abstract

Scalable Modeling and Measurement of TSV Applied for Efficiency Improvement of a RF PA

Jhong

Pan

et al. 2016

2016 IEEE 66th Electronic Components and Technology Conference (ECTC)

View full text Add to dashboard Cite

Scalable modeling of Through Silicon Vias up to milimeter-wave frequency

Cited by 3 publications

References 11 publications

Performance and process characteristic of glass interposer with through-glass-via(TGV)

Performance and process characteristic of glass interposer with through-glass-via(TGV)

Wideband and scalable equivalent-circuit model for differential through silicon vias with measurement verification

Scalable Modeling and Measurement of TSV Applied for Efficiency Improvement of a RF PA

Contact Info

Product

Resources

About