Scaling scenario of multi-level interconnects for future CMOS LSI

Abstract

The scaling guideline of the multi-level interconnects for future CMOS LSI is presented. It is based upon intensive circuit simulation combined with 2D field solver while considering wire length distribution of logic circuits. Interconnect structures such as metal aspect ratio and ILD thickness are optimized to minimize wiring delay without causing crosstalk problem. Furthermore, the scaling factors of future BEOL parameters are presented. IntroductionInterconnects have become the keys for the performance improvement of logic LSI because they affect the total performance such as speed, power and the chip size [1][2]. Especially, interconnect RC delay is the major performance

Fishbone

“…The cost is the possible non-convergence due to wrong early estimation. The problem of block-level routing is quite different from gate-level routing [4]. Usually the wiring density at the block level is not as high as the gate level.…”