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The scaling guideline of the multi-level interconnects for future CMOS LSI is presented. It is based upon intensive circuit simulation combined with 2D field solver while considering wire length distribution of logic circuits. Interconnect structures such as metal aspect ratio and ILD thickness are optimized to minimize wiring delay without causing crosstalk problem. Furthermore, the scaling factors of future BEOL parameters are presented. IntroductionInterconnects have become the keys for the performance improvement of logic LSI because they affect the total performance such as speed, power and the chip size [1][2]. Especially, interconnect RC delay is the major performance

A comparison between non-selfconsistent single-particle Monte Carlo (MC) simulations and measurements of the output characteristics of an 0.1 µm n-MOSFET is presented. First the bulk MC model, which features a new simplified treatment of inelastic acoustic intravalley scattering, is validated by comparison with experimental literature data for mobilities and velocities. The dopant distribution of the MOSFET is obtained from a 2D process simulation, which is calibrated with SIMS and electrical measurements and fine-tuned by a comparison of the measured transfer characteristics in the subthreshold regime with a coupled Schro¨dinger drift-diffusion (DD) simulation. Then the quantum effect is replaced by a shift of the work function and the DD, hydrodynamic (HD) and MC models are adjusted to reproduce the measured drain current in the linear regime. The results of the three models in the non-linear regime are compared without further adjustment to the measured output characteristics. While good agreement is found for the MC model, the on-current is significantly overestimated by the HD model and underestimated by the DD model.

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