Scan chain clustering for test power reduction

Elm, Melanie; Wunderlich, Hans-Joachim; Imhof, Michael E.; Zoellin, Christian G.; Leenstra, J.; Maeding, Nicolas

doi:10.1145/1391469.1391680

Cited by 21 publications

(9 citation statements)

References 26 publications

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“…Nonetheless, the difference is quite small when the rank threshold of the power-aware compression process is set to a high value. For all of the benchmarks examined, the proposed scheme delivers appreciable power reduction at the cost of a very small compression ratio loss for rank thresholds above 19.…”

Section: Resultsmentioning

confidence: 99%

“…It has been widely reported that uncontrolled scan power dissipation significantly degrades the scan test quality by incurring chip damage and overscreeninginduced yield loss [1]. While reducing power for non-compressed test vectors constitutes a formidable research challenge as exemplified by the number of research works published in the area [14]- [19], [29], the possibly conflicting compression goal elevates the challenge of power reduction to a highly challenging plane, as shown by the limited number of works on this topic [6], [24], [30]. The attainment of either target necessitates the appropriate utilization of the unspecified bits (don't cares) in the test cubes.…”

Section: Introductionmentioning

confidence: 99%

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Scan Power Reduction for Linear Test Compression Schemes Through Seed Selection

Chen

Orailoğlu

2012

IEEE Trans. VLSI Syst.

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XOR network-based on-chip test compression schemes have been widely employed in large industrial scan designs due to their high compression ratio and efficient decompression mechanism. Nevertheless, such a scheme necessitates high unspecified bit ratios in the original test cubes, resulting in quite significant difficulties in preprocessing test cubes for scan power reduction. The linear mapping from the original cubes to the compressed seeds typically provides extra degrees of flexibility as multiple seeds may reconstruct the test cube. Due to the highly divergent power impact of distinct seeds though, appreciable power reductions in the decompressed test data can be attained through the pinpointing of the power-optimal seeds during the compression phase. This work explores the aforementioned flexibility in the seed space, and outlines a mathematical and algorithmic framework for a poweraware linear test compression scheme. The proposed technique incurs no hardware overhead over the traditional linear compression scheme; it can be easily embedded furthermore into the industrial test compaction/compression flow. Experimental results confirm that the proposed technique delivers significant scan power reduction with negligible impact on the compression ratio.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Scan Power Reduction for Linear Test Compression Schemes Through Seed Selection

Chen

Orailoğlu

2012

IEEE Trans. VLSI Syst.

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“…The technique in [16] focuses on the ratio of care bits in a scan chain and reduces shift power by enabling scan chains that are ineffective for detecting new faults during scan shift. To improve this technique, the approach in [17] clusters the scan chains into several groups and achieves more significant shift power reduction by limiting scan shift to a portion of groups with mask logics during scan shift. The researchers in [18,23,24] [19].…”

Section: Introductionmentioning

confidence: 99%

Reducing Test Power and Improving Test Effectiveness for Logic BIST

Wang¹,

Cai²,

Xiang³

2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Excessive power dissipation is one of the major issues in the testing of VLSI systems. Many techniques are proposed for scan test, but there are not so many for logic BIST because of its unmanageable randomness. This paper presents a novel low switching activity BIST scheme that reduces toggle frequency in the majority of scan chain inputs while allowing a small portion of scan chains to receive pseudorandom test data. Reducing toggle frequency in the scan chain inputs can reduce test power but may result in fault coverage loss. Allowing a small portion of scan chains to receive pseudorandom test data can make better uniform distribution of 0 and 1 and improve test effectiveness significantly. When compared with existing methods, experimental results on larger benchmark circuits of ISCAS'89 show that the proposed strategy can not only reduce significantly switching activity in circuits under test but also achieve high fault coverage.

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“…The approach in [3] clusters the scan chains into several groups and reduces shift power by enabling ineffective ones with mask logics during scan shift. Technique presented in [4] reduces test power by inserting extra logic gates to freeze the outputs of the scan flip-flops during scan operation.…”

Section: Introductionmentioning

confidence: 99%

Low power logic BIST with high test effectiveness

Wang

Liu

Cai

et al. 2013

IEICE Electron. Express

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Excessive test power has been a serious concern in BIST techniques. Shift power consumption can be significantly reduced by increasing the correlation among adjacent test data bits. However, this method may cause fault coverage loss. This paper presents a novel low power BIST scheme that reduces toggle probability of the scan input data while only shifting out part of capture responses for fault analysis and using the rest of capture responses as new test data. Using part of capture responses as test data can improve uniform distribution of 1 s and 0 s in test stimulus bits and thus result in high test effectiveness. Experimental results on larger benchmark circuits of ISCSAS89 and ITC99 show that the proposed strategy can reduce significantly test power while suppressing test coverage loss.

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Scan chain clustering for test power reduction

Cited by 21 publications

References 26 publications

Scan Power Reduction for Linear Test Compression Schemes Through Seed Selection

Scan Power Reduction for Linear Test Compression Schemes Through Seed Selection

Reducing Test Power and Improving Test Effectiveness for Logic BIST

Low power logic BIST with high test effectiveness

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