ScanBist A Multi-frequency Scan-Based BIST Method

Nadeau-Dostie, B.; Burek, D.; Hassan, A.S.M.

doi:10.1109/test.1992.527862

Cited by 9 publications

(2 citation statements)

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“…It then serially shifts nppropriatc data into Uie compare data inputs and samples the RAM read-only output signals for the CAM and RAM test algorithms discussed in section 111.This architecture takes advantage of boundary scan, cache memory BIS'I' and ScanRist[5] testing to verify all~o q m data m p l pm rcai only L W p I p n s Fig. 3.…”

mentioning

confidence: 99%

A high speed embedded cache design with non-intrusive BIST

Kornachuk

McNaughton²,

Gibbins³

et al.

Proceedings of IEEE International Workshop on Memory Technology, Design, and Test

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This paper describes a 155 MHz wide-word cache design and ifs test integration features. Design techniques f o r high speed CAM with single ended niarch line sensing and highly integruted RAM are described. A new cache BIST algorithm bused on the SMARCH [ I ] algorithm is presented. New techniques are described for the insertion of cache BIST access points into a high speed data path wifhoiit compromising mission mode performunce. Perfortnance results of cache tnetnory used for telecotntnunications microprocessor applications with 1Kb of CAM referencing a 5 Kb RAM are presented.

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confidence: 99%

A high speed embedded cache design with non-intrusive BIST

Kornachuk

McNaughton²,

Gibbins³

et al.

Proceedings of IEEE International Workshop on Memory Technology, Design, and Test

Self Cite

View full text Add to dashboard Cite

show abstract

“…Pseudo-exhaustive BIST is used for very high fault coverages (99+%); whereas the pseudorandom test oriented methods were often augmented with test point insertion to achieve the required fault coverage[71[8]. Structured Test Method…”

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confidence: 99%