Sea of leads compliant I/O interconnect process integration for the ultimate enabling of chips with low-k interlayer dielectrics

Bakir, Muhannad S.; Dang, Bing; Emery, R.D.; Vandentop, Gilroy; Kohl, Paul A.; Meindl, J.D.

doi:10.1109/tadvp.2005.848386

Cited by 16 publications

(5 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Closepacked, direct solder attachment of ICs onto a high-density substrate has cost, performance, size, and weight benefits; however, it creates mechanical stresses during chip assembly and in-service thermal cycling due to the mismatch in coefficient of thermal expansion (CTE) between the silicon die (CTE ¼ 3 ppm/ C) and FR4 or other organic substrates and PCBs (CTE about 17 ppm/ C). Bakir et al demonstrated the fabrication of mechanically compressible air gaps which can provide strategic stress relief points [12]. Figure 3(a) shows a mechanically compliant I/O built onto a test chip with 12,000 x-y-z compliant leads per cm 2 [12][13][14][15].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Decomposable and Template Polymers: Fundamentals and Applications

Uzunlar

Schwartz

Phillips

et al. 2016

Journal of Electronic Packaging

View full text Add to dashboard Cite

Polymers can be used as temporary place holders in the fabrication of embedded air gaps in a variety of electronic devices. Embedded air cavities can provide the lowest dielectric constant and loss for electrical insulation, mechanical compliance in devices where low-force deformations are desirable, and can temporarily protect movable parts during processing. Several families of polymers have been used as sacrificial, templating polymers including polycarbonates, polynorbornenes (PNBs), and polyaldehydes. The families can be distinguished by chemical structure and decomposition temperature. The decomposition temperature ranges from over 400 °C to below room temperature in the case of low ceiling temperature polymers. Overcoat materials include silicon dioxide, polyimides, epoxy, and bis-benzocyclobutene (BCB). The methods of air-gap fabrication are discussed. Finally, the use of photoactive compounds in the patterning of the sacrificial polymers is reviewed.

show abstract

Section: Introductionmentioning

confidence: 99%

“…Bakir et al demonstrated the fabrication of mechanically compressible air gaps which can provide strategic stress relief points [12]. Figure 3(a) shows a mechanically compliant I/O built onto a test chip with 12,000 x-y-z compliant leads per cm 2 [12][13][14][15]. An individual connection (magnification of Fig.…”

Section: Introductionmentioning

confidence: 99%

Decomposable and Template Polymers: Fundamentals and Applications

Uzunlar

Schwartz

Phillips

et al. 2016

Journal of Electronic Packaging

View full text Add to dashboard Cite

show abstract

“…Recently, the LAG structure has been integrated into commercial IC products by Intel and AMD to allow an easy replacement of the processor [3]. To address the thermal expansion mismatch at the contact surface between the chip and board, a Sea of Leads (SoLs) structure was proposed, fabricated, and successfully assembled to the manufacture process [8,9]. In [10], a cost-effective fabrication process for innovative Flex-Connects was reported, and systematic mechanical and electrical simulations were carried out to verify its reliability.…”

Section: Introductionmentioning

confidence: 99%

Multiphysics Analysis and Optimal Design of Compressible Micro-Interconnect for 2.5D/3D Heterogeneous Integration

et al. 2021

View full text Add to dashboard Cite

Compressible Micro-Interconnect (CMI) shows tremendous potential in 2.5D/3D heterogeneous integration due to its outstanding performance in integration, electrical isolation, and thermal management. In this work, an optimal design approach for CMIs is developed based on a coupling framework of multiphysics simulation and particle swarm optimization (PSO). In the framework, the mechanical simulation was conducted firstly to obtain the stress distributions as CMI switched from the initial state to the working position. The contact resistance between CMI and the top pad was modeled and quantitively analyzed. Subsequently, the PSO method was utilized to implement the structural optimization of CMI to improve the performance. Multiphysics simulations of both the original and optimized CMIs were carried out and compared. With the implementation of the optimized CMIs, the contact resistance dropped from 155.3 mΩ to 108.8 mΩ, which brought significant improvement in both DC voltage drop and self-heating effect. The influence of the self-heating effect on the electrical performance of CMI is also discussed qualitatively.

show abstract

“…Due to the compliance of the structure, the stress caused by CTE mismatch can be mitigated. Various compliant interconnect structures have been researched in the last few decades, including micro-spring [4]- [6], micro-helix [7], sea of leads [8], and sea of polymer pillars [9]. Additionally, compliant interconnects are advantageous for mounting chips onto non-planar surface.…”

Section: Introductionmentioning

confidence: 99%

Flip chip based on compliant double helix interconnect for high frequency applications

Hernandez

Wang

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

View full text Add to dashboard Cite

Compliant interconnects are a viable solution for coefficient of thermal expansion (CTE) mismatch failures and it is therefore important to understand their performance at high frequency. In this work, we present double helix shaped compliant interconnects that are designed and fabricated on top of a coplanar waveguide (CPW) test structure followed by flip chip bonding. The high frequency performance of compliant double helix interconnect is simulated and measured. The measured insertion and reflection loss were less than -0.6 dB and -15 dB up to 50 GHz, respectively.

show abstract

Sea of leads compliant I/O interconnect process integration for the ultimate enabling of chips with low-k interlayer dielectrics

Cited by 16 publications

References 14 publications

Decomposable and Template Polymers: Fundamentals and Applications

Decomposable and Template Polymers: Fundamentals and Applications

Multiphysics Analysis and Optimal Design of Compressible Micro-Interconnect for 2.5D/3D Heterogeneous Integration

Flip chip based on compliant double helix interconnect for high frequency applications

Contact Info

Product

Resources

About