Self Heating Simulation of Multi-Gate FETs

Abstract

Due to material properties and geometric aspects self heating simulation of silicon devices requires 3D simulation of large structures. Fully coupled electrothermal simulation in three spatial dimensions is extremely memory and CPU time intensive. This work demonstrates a simplification of the approach to a thermal only problem from which much useful information can be extracted. We have applied this approach to a typical trigate device on SOI substrate. The simulated thermal resistance is in reasonable agreement with measurements. Parameters for the width dependent compact model for the thermal resistance can readily be extracted. The dependence of thermal resistance on the thickness of the bottom oxide has also been investigated. Moreover this permits transient behavior to be simulated in much more detail than is possible to be measured experimentally. Thus time constants and thermal capacitances for thermal compact models which are usually difficult to extract experimentally may be simulated numerically.

Silicon‐on‐insulator MOSFETs models in analog/RF domain

“…Molzer et al . also used numerical simulations and considered the thermal resistance dependence on the number of parallel fins. Braccioli et al .…”

“… performed electro‐thermal simulations to study the dependence of FinFET thermal properties on BOX thickness, source and drain extensions length, fin spacing, and fin height. However, analysis of the thermal properties in is not supported by experimental results and is entirely based on numerical simulations that require certain assumptions about heat conduction paths, device symmetries, and boundary conditions. Experimental work on self‐heating in FinFETs and UTBBs was carried out, respectively in and in .…”

Analog circuits using FinFETs: benefits in speed-accuracy-power trade-off and simulation of parasitic effects

“…Using the equivalent circuit model, the impact of SH on Fin-FET circuits is investigated. R th is obtained from simulations as described above, C th from measurement and device simulations (Molzer et al, 2006) revealing a time constant of about 100ns and a maximum current reduction of about 10%. First a single-ended two stage OTA as presented above is analyzed in terms of it's transient response.…”

Analysis on Self-Heating Effect in 7 nm Node Bulk FinFET Device

“…This results in poor electrothermal characteristics although 3D devices have better electrostatic performance than conventional planar devices [3,4] due to short channel effect (SCE) suppression. Thus far, the studies on SHE of silicon-oninsulator (SOI) FinFETs due to their inferior heat transfer caused by low thermal conductivity of SiO 2 have mainly been conducted by many groups [5,6]. However, as device is extremely scaled under 10 nm node, SHE on bulk FinFET becomes important since the thermal conductivity in narrow structure becomes much smaller as device is continuously scaling [7][8][9].…”