Self-Substrate-Triggered Technique to Enhance Turn-On Uniformity of Multi-Finger ESD Protection Devices

Ker, Ming‐Dou; Chen, Jia-Huei

doi:10.1109/jssc.2006.883331

Cited by 42 publications

(20 citation statements)

References 19 publications

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“…Figure 6 shows the TLP I-V curves of the embedded 2-finger MOSFET in NSCR and PSCR, and the 4-finger conventional GGNMOS and GDPMOS. The MOSFET can conduct homogeneously if its second breakdown voltage is higher than its trigger voltage [9]. That is verified in our test.…”

Section: Test Resultssupporting

confidence: 76%

A novel SCR structure integrated with power clamp for ESD protection at I/O pad

Fan

Jiang

Zhang

2012

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology

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A novel area-efficient SCR structure is proposed for ESD protection at I/O pad. It is composed of two complementary SCR devices. Both of them can be triggered not only by the breakdown in embedded MOSFET like LVTSCR, but also by the parasitic capacitor between VDD and VSS. Besides, the embedded MOSFET in the novel structure can provide basic ESD protection between VDD and VSS at the cost of little additional area. The N+ and P+ connecting to I/O pad can be isolated well in normal circuit operation to enhance their latch up immunity.

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Section: Test Resultssupporting

confidence: 76%

A novel SCR structure integrated with power clamp for ESD protection at I/O pad

Fan

Jiang

Zhang

2012

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology

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“…Thirdly, the ESD robustness is not proportional to the total width of LDNMOS due to its low V hold , because the conducting part would clamp the voltage applied to the whole LDNMOS until this part is burned out first or other part turns on [9]. In other words, a larger width protection device may not lead to higher ESD robustness.…”

Section: Introductionmentioning

confidence: 99%

A Method to Prevent Strong Snapback in LDNMOS for ESD Protection

Fan

Jiang

Zhang

2013

IEEE Trans. Device Mater. Relib.

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High injection electron current in an LDNMOS can lead to a strong snapback and latch-up-like characteristic. It is susceptible to latch-up-like in high-voltage ICs, if its holding voltage is lower than the power supply voltage. A method to raise the LDNMOS holding voltage is proposed and verified in a 0.35-μm 20-V/5-V BCD process without additional masks. It is realized by adding a relative high doping Nw provided for a 5-V PMOS in the drain region. The doping concentration in the Nw is higher than the injection electron density from the source under ESD stress. The Nw can extend the length of the space-charge region and lead to a higher voltage drop and high strong snapback current. This way, we get an LDNMOS with holding voltage higher than 24 V.Index Terms-ESD, high holding voltage, LDNMOS.

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“…:!! :-:::: t:::': =J In order to effectively solve the non-uniform turned-on problem, a considerable number of literatures [6][7][8][9][10][11][12][13][14] to investigate the substrate pick-up process to solve the problem.…”

Section: Introductionmentioning

confidence: 99%

Influences of source pick-up and well engineering on the ESD robustness of LV process nMOSTs

Chen

Lee

Lai

et al. 2013

2013 1st International Future Energy Electronics Conference (IFEEC)

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Usually a MOST of I/O cells in integrated circuits will be in the form of multi-finger type. However, the non-uniform turned on phenomenon in an MOST is deeply affecting the ESD reliability robustness. Here, the impacts of pick-up stripe variation and a pWell structure adding are investigated in this paper. ESD performance of these nMOSTs fabricated by a O.351lm CMOS process is evaluated in this work. Nevertheless, it is desirous to improve the ESD capability of ESD elements. After a systematic analysis, it is found that no matter what kind of channel length of nMOSTs, the p + pick-up structure of source side and p-well structure in the O.351lm LV process are poor contributors to 1 t2 robustness of elements, i.e., the substrate pick-up/ p-well structures will obviously lower the 1 t2 level. Therefore, the source end should avoid adding any p + pick-up stripe and any p-well structure in the O.351lm process.

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Self-Substrate-Triggered Technique to Enhance Turn-On Uniformity of Multi-Finger ESD Protection Devices

Cited by 42 publications

References 19 publications

A novel SCR structure integrated with power clamp for ESD protection at I/O pad

A novel SCR structure integrated with power clamp for ESD protection at I/O pad

A Method to Prevent Strong Snapback in LDNMOS for ESD Protection

Influences of source pick-up and well engineering on the ESD robustness of LV process nMOSTs

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