Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs

Shulaker, Max M.; Rethy, Jelle Van; Hills, Gage; Wei, Hai; Chen, Hongyu; Gielen, Georges; Wong, H.-S. Philip; Mitra, Subhasish

doi:10.1109/jssc.2013.2282092

Cited by 53 publications

(48 citation statements)

References 44 publications

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“…The difference in the set and reset curves between the 1T1R structures including the silicon-FET versus the CNFET is attributed to the CNFET not exhibiting the same saturation in the I D -V DS characteristics as the silicon-FET (Fig. 7-8, these CNFETs saturate at higher V DS due to un-optimized source and drain contact resistance, similar to previously reported I D -V DS CNFET characteristics [12,13]). While Fig.…”

Section: Fabrication Processsupporting

confidence: 85%

“…The CNFET can successfully be used to both set the compliance current for the set operation of the RRAM, and can be used as a pass-gate to select whether or not to perform the reset operation of the RRAM. These operations can be only performed after VMR is used to selectively remove >99.99% metallic CNTs, resulting in >5,000 I ON /I OFF for the CNFET, while inadvertently removing <4% semiconducting CNTs [12] and therefore retaining enough I ON to perform the RRAM reset. …”

Section: Fabrication Processmentioning

confidence: 99%

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Monolithic 3D integration of logic and memory: Carbon nanotube FETs, resistive RAM, and silicon FETs

Shulaker

Pal

et al. 2014

2014 IEEE International Electron Devices Meeting

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130

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We demonstrate monolithic 3D integration of logic and memory in arbitrary vertical stacking order with the ability to use conventional inter-layer vias to connect between any layers of the 3D IC. We experimentally show 4 vertically-stacked layers (logic layer followed by two memory layers followed by another logic layer), enabled by the integration of traditional silicon-FETs (on the bottom-most layer) with low-processing-temperature emerging nanotechnologies: metal-oxide resistive random-access memory (RRAM), and carbon nanotube-FETs (CNFETs). As a demonstration, we show a routing element of a switchbox for a field-programmable gate array (FPGA), with each component of the routing element (involving both logic and memory elements) on their own vertical layer. Introduction Monolithic Three-Dimensional IntegrationThree-dimensional (3D) integration is a promising technology option for improving the performance, energy efficiency, and footprint of electronic systems [1]. Today's 2.5D and 3D integration are achieved through chip-stacking, with multiple vertical circuit layers connected using Through-Silicon Vias (TSVs). Monolithic 3D integration, whereby each circuit layer is thin and is fabricated directly over the previous circuit layers on the same substrate, can use conventional inter-layer vias (ILVs) to connect between various layers. The use of conventional vias rather than TSVs allows for massive vertical interconnect density, potentially maximizing the benefits of 3D integrated circuits (ICs) [1]. Moreover, monolithic 3D integration of logic and memory can enable new architectures and potentially alleviate the logic-memory communication bottleneck [2,3].

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Section: Fabrication Processsupporting

confidence: 85%

Section: Fabrication Processmentioning

confidence: 99%

Monolithic 3D integration of logic and memory: Carbon nanotube FETs, resistive RAM, and silicon FETs

Shulaker

Pal

et al. 2014

2014 IEEE International Electron Devices Meeting

Self Cite

130

View full text Add to dashboard Cite

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“…With a sufficient source-drain bias, the metallic CNTs pass enough current that they breakdown due to a Joule self-heating process. Electrical breakdown has been shown to selectively remove >99.99% of all metallic CNTs with inadvertent removal of <4% semiconducting CNTs [20]. It can be applied wafer-scale, rendering the process compatible for VLSI applications [19,20].…”

Section: Electrical Measurements: High Current-drive Cnfetsmentioning

confidence: 99%

“…Electrical breakdown has been shown to selectively remove >99.99% of all metallic CNTs with inadvertent removal of <4% semiconducting CNTs [20]. It can be applied wafer-scale, rendering the process compatible for VLSI applications [19,20]. After electrical breakdown, the average CNFET I ON is 84 µA/µm with an I ON /I OFF of 5,660.…”

Section: Electrical Measurements: High Current-drive Cnfetsmentioning

confidence: 99%

High-performance carbon nanotube field-effect transistors

Shulaker

Pitner

Hills

et al. 2014

2014 IEEE International Electron Devices Meeting

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“…For the timebased implementation, a Capacitance-Controlled (Ring) Oscillator (CCO) is used as a sensor-to-time conversion element (Fig. 2c) [6,10,11]. It is important to note that in the following derivation only thermal noise is taken into account in order to determine the theoretical limits.…”

Section: Capacitive Sensor Interfacingmentioning

confidence: 99%

Towards Energy-Efficient CMOS Integrated Sensor-to-Digital Interface Circuits

Rethy¹,

Smedt²,

Dehaene³

et al. 2014

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

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The ever increasing demand for improved autonomy in wireless sensor devices, drives the search for new energy-efficient sensor interface topologies in CMOS technology. Recently, time-based conversion has gained a lot of interest due to its high potential to implement highly-digital circuitry. While voltage-based analog integrated circuits suffer from the decreased supply voltage and voltage swing in highly-scaled CMOS technologies, time-based processing takes advantage of the increased timing resolution. However, how do these time-based sensor interface circuits compare to their amplitude-based counterparts fundamentally? To answer this question, theoretical limits are derived in this chapter for both implementations, which shows that the sensor itself is actually the dominant factor in limiting the achievable energy efficiency. Time-based topologies, however, enable the implementation of highly-digital interfaces, which are scalable, areaefficient and have low-voltage potential. These observations are illustrated with several practical designs.

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Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs

Cited by 53 publications

References 44 publications

Monolithic 3D integration of logic and memory: Carbon nanotube FETs, resistive RAM, and silicon FETs

Monolithic 3D integration of logic and memory: Carbon nanotube FETs, resistive RAM, and silicon FETs

High-performance carbon nanotube field-effect transistors

Towards Energy-Efficient CMOS Integrated Sensor-to-Digital Interface Circuits

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