SEU resistance in advanced SOI-SRAMs fabricated by commercial technology using a rad-hard circuit design

Hirose, Kazuyuki; Saito, Hirobumi; Kuroda, Yoshihiro; Ishii, Shigeru; Fukuoka, Yoshihiro; Takahashi, Daisuke

doi:10.1109/tns.2002.805978

Cited by 78 publications

(28 citation statements)

References 13 publications

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“…Furthermore, FD-SOI-CMOS devices have resistance characteristics against high energy particle radiation. Hirose et al [29], [30] have shown that 128-Kbit SRAMs using a rad-hard circuit design in a 0.2 μm FD-SOI-CMOS process have high tolerance for Single Event Latch up, Single Event Upset, and Total Ionizing Dose. Low power VLSI with high tolerance for temperature variation and high energy particle radiation should be useful for various scientific field including space explorations or astronomy.…”

Section: Discussionmentioning

confidence: 99%

Development of Cryogenic Readout Electronics for Far-Infrared Astronomical Focal Plane Array

Nagata

Wada

Ikeda

et al. 2011

IEICE Trans. Commun.

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SUMMARYWe have been developing low power cryogenic readout electronics for space borne large format far-infrared image sensors. As the circuit elements, a fully-depleted-silicon-on-insulator (FD-SOI) CMOS process was adopted because they keep good static performance even at 4.2 K where where various anomalous behaviors are seen for other types of CMOS transistors. We have designed and fabricated several test circuits with the FD-SOI CMOS process and confirmed that an operational amplifier successfully works with an open loop gain over 1000 and with a power consumption around 1.3 μW as designed, and the basic digital circuits worked well. These results prove that the FD-SOI CMOS process is a promising candidate of the ideal cryogenic readout electronics for farinfrared astronomical focal plane array sensors.

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Section: Discussionmentioning

confidence: 99%

Development of Cryogenic Readout Electronics for Far-Infrared Astronomical Focal Plane Array

Nagata

Wada

Ikeda

et al. 2011

IEICE Trans. Commun.

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“…At the circuit level, increasing the critical charge of a circuit node and adding transistors to enable redundant storage of information are two main approaches to reduce the effects of soft errors [2]- [5]. These techniques tend to increase the power consumption and lower the speed of the circuits [6]- [8].…”

Section: Introductionmentioning

confidence: 99%

Rad-Hard 32 nm FinFET Based Inverters

Rathod

Saxena

Dasgupta

2009

2009 Annual IEEE India Conference

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This paper reports a novel circuit level hardening technique that can decrease sensitivity to radiation induced single event upsets in 32nm FinFET based circuits. Five different types of 32 nm FinFET based inverters are analyzed. Proposed design outperforms over the unhardened circuit when exposed to radiation. This is majorly due to the innovative design technique used to neutralize effect of single event upset without affecting normal operation. Effect of back gate voltage and back gate oxide thickness variation is reported. Results indicate that the proposed design has good hardness to single event upset but has little area and power overheads than the unhardened FinFET based design.

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“…Moreover SOI devices are located on a very thin silicon layer, the energy deposit by an impinging particle is relatively small, and, then, it appears that we can automatically mitigate the single event upsets (SEU) and/or single-event transients (SET). The reality is that the SEU and/or SET effects are not necessarily eliminated even in an advanced SOI process [1,2] without adoption of an appropriate hardening-by-design technology.…”

Section: Introductionmentioning

confidence: 99%