Two types of 4H-silicon carbide (SiC) MOSFETs are proposed in this paper. One is the novel designed V-groove trench MOSFET that utilizes the 4H-SiC (0-33-8) face for the channel region. The MOS interface using this face shows the extremely low interface state density (D it ) of 3 × 10 11 cm −2 eV −1 , which causes the high channel mobility of 80 cm 2 V −1 s −1 results in very low channel resistance. The buried p + regions located close to the trench bottom can effectively alleviate the electric field crowding without the significant sacrifice of the increase of the resistance. The low specific ON-state resistance of 3.5 m cm 2 with sufficiently high blocking voltage of 1700 V is obtained. The other is the double implanted MOSFET with the carefully designed junction termination extension and field-limiting rings for the edge termination region, and the additional doping into the junction FET region. With a high-quality and high-uniformity epitaxial layer, 6 mm × 6 mm devices are fabricated. The well balanced specific ON-state resistance of 14.2 m cm 2 and the blocking voltage of 3850 V are obtained for 3300 V application.
Index Terms-(0-33-8) face, 4H-silicon carbide (SiC), buried p + region, channel mobility, field-limiting ring (FLR), junction FET (JFET), junction termination extension (JTE), MOSFET, V-groove trench.Yasuki Mikamura received the B.E. and M.E. degrees in electrical engineering from Kyoto University, Kyoto, Japan, in 1983 and 1985, respectively.