Two types of 4H-silicon carbide (SiC) MOSFETs are proposed in this paper. One is the novel designed V-groove trench MOSFET that utilizes the 4H-SiC (0-33-8) face for the channel region. The MOS interface using this face shows the extremely low interface state density (D it ) of 3 × 10 11 cm −2 eV −1 , which causes the high channel mobility of 80 cm 2 V −1 s −1 results in very low channel resistance. The buried p + regions located close to the trench bottom can effectively alleviate the electric field crowding without the significant sacrifice of the increase of the resistance. The low specific ON-state resistance of 3.5 m cm 2 with sufficiently high blocking voltage of 1700 V is obtained. The other is the double implanted MOSFET with the carefully designed junction termination extension and field-limiting rings for the edge termination region, and the additional doping into the junction FET region. With a high-quality and high-uniformity epitaxial layer, 6 mm × 6 mm devices are fabricated. The well balanced specific ON-state resistance of 14.2 m cm 2 and the blocking voltage of 3850 V are obtained for 3300 V application. Index Terms-(0-33-8) face, 4H-silicon carbide (SiC), buried p + region, channel mobility, field-limiting ring (FLR), junction FET (JFET), junction termination extension (JTE), MOSFET, V-groove trench.Yasuki Mikamura received the B.E. and M.E. degrees in electrical engineering from Kyoto University, Kyoto, Japan, in 1983 and 1985, respectively.

The characteristics of surface acoustic waves propagating on a three-layered structure consists of a piezoelectric ZnO film, a piezoelectric AIN film, and a Kovar glass sheet have been studied. Both theoretical and experimental results have shown that the first-mode leaky surface acoustic wave has a high volocity (V,,), a high coupling coefficient ( k ' ) , a small temperature coefficient of frequency (TCF), and a tolerably small propagation loss (PL) when the product of the wavenumber and the film thickness ( K H ) o f the ZnO film is around 1.0. The phase velocity dispersion to KH of AIN is also very small at KH of ZnO of 1.0. The experimental results show that V,, of 5840 mls, /c2 of 4.37 percent, TCF of +21.0 ppm/"C and P , smaller than 10 dB/ cm at 97 MHz are simultaneously attained at KH of ZnO of 1.05 and K H of AIN of 1.5.

The influence of surface pit shape on 4H-SiC double implanted MOSFETs (DMOSFETs) reliability under a high temperature drain bias test has been investigated. Threading dislocations formed two types of pit shapes (deep pit and shallow pit) on an epitaxial layer surface. The cause of the failure was revealed to be an oxide breakdown above the pit generated at the threading mixed dislocation in both pit shapes. Weibull distributions between two types of pits were different. Although the DMOSFETs on the epitaxial layer with the deep pit show longer lifetime than those with the shallow pit, the epitaxial layer with the shallow pit is suitable to estimate the lifetime of the DMOSFETs because of a linearity of the Weibull plot. The lifetime of the DMOSFETs with the shallow pit was dominated by an oxide electric field. The maximum oxide electric field required to obtain the lifetime of more than 10 years was estimated to be 2.7 MV/cm.

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V-groove trench MOSFETs with the 4H-SiC{0-33-8} face as the trench sidewall for the channel region have been investigated. The on-resistance and breakdown voltage strongly depend on the aperture ratio of the buried p + regions. The VMOSFETs with the buried p + regions of 71% on a 6-inch wafer exhibited a low specific on-resistance of 2.0 m cm 2 with 1200 V blocking voltage. The threshold voltage is 2.3 V at 175 o C, which shows the VMOSFETs have tolerability for an erroneous ignition under high temperature. The switching capability showed low switching losses over DMOSFETs on 4 o off 4H-SiC(0001) face and normal operation under fast switching repetitive test (40 Vns -1 ). The stability of the threshold voltage was demonstrated by HTGB tests. I.978-1-4799-6261-7/15/$31.00 ©2015 IEEE