SiGe BiCMOS Technology for RF Circuit Applications

Racanelli, M.; Kempf, P.

doi:10.1109/ted.2005.850696

Cited by 52 publications

(19 citation statements)

References 11 publications

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“…To investigate how this performance compares with that achieved for conventional lateral MOSFETs at the same 0.5-μm lithography node, Fig. 10 plots f T as a function of technology node for a variety of conventional planar RF technologies taken from [26]. It can be seen that our 80-nm silicided v-MOSFET delivers a significantly higher f T than comparable planar MOSFET technologies implemented using the same 0.5-μm lithography.…”

Section: Discussionmentioning

confidence: 98%

Self-Aligned Silicidation of Surround Gate Vertical MOSFETs for Low Cost RF Applications

Hakim

Tan

Abuelgasim

et al. 2010

IEEE Trans. Electron Devices

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Section: Discussionmentioning

confidence: 98%

Self-Aligned Silicidation of Surround Gate Vertical MOSFETs for Low Cost RF Applications

Hakim

Tan

Abuelgasim

et al. 2010

IEEE Trans. Electron Devices

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“…SiGe (Silicon-Germanium) technology has major benefits over GaAs in high-speed applications. SiGe BiCMOS (Bipolar Complementary Metal-Oxide Semiconductor) technology also fulfils high-level integration requirements of beamforming systems [43].…”

Section: Rf Design For 5gmentioning

confidence: 99%

Design for Smaller, Lighter and Faster ICT Products: Technical Expertise, Infrastructures and Processes

Aydın¹,

Uçar²

2017

Adv. sci. technol. eng. syst. j.

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“…The working principle of HBTs and the review work are given in detail in [1][2][3][4][5]. Several works have been reported on BiCMOS technology on bulk substrate that can be found from the literature [6][7][8]. Although BiCMOS technology on bulk substrate offers devices with promising performance, the process complexity, isolation among devices and power consumption have been the main issues in deep submicron lithography nodes.…”

Section: Introductionmentioning

confidence: 99%

Epilayer Optimization of NPN SiGe HBT with n+ Buried Layer Compatible With Fully Depleted SOI CMOS Technology

Misra

Qureshi²

2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this paper, the epi layer of npn SOI HBT with n+ buried layer has been studied through Sentaurus process and device simulator. The doping value of the deposited epi layer has been varied for the npn HBT to achieve improved f t BV CEO product (397 GHzV). As the BV CEO value is higher for low value of epi layer doping, higher supply voltage can be used to increase the f t value of the HBT. At 1.8 V V CE , the f t BV CEO product of HBT is 465.5 GHzV. Further, the film thickness of the epi layer of the SOI HBT has been scaled for better performance (426.8 GHzV f t BV CEO product at 1.2 V V CE ). The addition of this HBT module to fully depleted SOI CMOS technology would provide better solution for realizing wireless circuits and systems for 60 GHz short range communication and 77 GHz automotive radar applications. This SOI HBT together with SOI CMOS has potential for future high performance SOI BiCMOS technology.

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SiGe BiCMOS Technology for RF Circuit Applications

Cited by 52 publications

References 11 publications

Self-Aligned Silicidation of Surround Gate Vertical MOSFETs for Low Cost RF Applications

Self-Aligned Silicidation of Surround Gate Vertical MOSFETs for Low Cost RF Applications

Design for Smaller, Lighter and Faster ICT Products: Technical Expertise, Infrastructures and Processes

Epilayer Optimization of NPN SiGe HBT with n+ Buried Layer Compatible With Fully Depleted SOI CMOS Technology

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