Sigma-delta column-wise A/D conversion for cooled ROIC

Guellec, Fabrice; Villard, P.; Rothan, Frederic; Alacoque, Laurent; Chancel, C.; Martin, P.; Castelein, Pierre; Maillart, Patrick; Pistone, Frédéric; Costa, Pedro da

doi:10.1117/12.719171

Cited by 19 publications

(9 citation statements)

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“…Also for the 2nd-order converter presented in [5] monotony of the output could not be guaranteed and a comparatively complex decimation filter is needed. For the converter published in [8] no prediction regarding monotony can be made.…”

Section: Benefits Of the Mmamentioning

confidence: 99%

“…In [7] a 12-bit 2nd-order incremental Sigma-Delta data converter (I-ΣΔ-DC) has been compared to a SAR-ADC. Another 12-bit 2nd-order I-ΣΔ-DC for a focal plane array was presented in [5]. A 1st-order ΣΔ-ADC optimized for CMOS imager was published in [8].…”

Section: Introductionmentioning

confidence: 99%

“…SAR and cyclic ADCs are much faster than single-slope types but require complex circuitry for higher resolutions [3]. Due to capacitance mismatch it is difficult to achieve resolutions above 10-bit with uncalibrated SAR converters [5].…”

Section: Introductionmentioning

confidence: 99%

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A low-power continuous-time incremental 2nd-order-MASH ΣΔ-modulator for a CMOS imager

Uhlig

Schüffny

Neubauer

et al. 2009

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)

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This paper presents a novel ΣΔ-modified MASH architecture (MMA) for a CMOS imager. This architecture makes use of a 1st-order incremental continuous-time Sigma-Delta modulator with 1.5-bit internal quantizer. It shows key benefits regarding efficient decimation and reduced circuit complexity compared to conventional ΣΔ-Architectures. Theory of operation, impact of non-idealities, implementation issues and benefits of the new architecture are depicted. The implementation of the MMA in an 180nm CMOS-Process and simulation results are presented.

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Section: Benefits Of the Mmamentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A low-power continuous-time incremental 2nd-order-MASH ΣΔ-modulator for a CMOS imager

Uhlig

Schüffny

Neubauer

et al. 2009

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)

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“…First order incremental ΣΔ modulators have simple architectures but low speed: a 13-bit resolution would require 2 13 clock cycles per conversion which corresponds to high clock frequency and large power consumption [4]. Higher order incremental ADC can give the needed resolution at a modest clock frequency but requires a decimation filter which would occupy large silicon area and consume large power [5].…”

Section: Introductionmentioning

confidence: 99%

A 13-bit, low-power, compact ADC suitable for sensor applications

Chen

Shen

et al. 2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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A 100μW, 13bit ADC used for sensor array applications is presented in this paper. The ADC employs an extended counting architecture in which the residual error from a first-order incremental ΣΔ modulator is encoded by a cyclic ADC to achieve high accuracy at a relatively high speed. Hardware reuse technique is utilized for low power consumption and small silicon area. The prototype ADC is implemented in 0.18μm CMOS technology with 1.8V supply voltage and the core area is only 0.06mm 2 including control logic. The ADC shows a peak SNDR/SFDR of 65.4dB/71.9dB.

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“…Although column parallel architectures are very common [4,5] ,pixel parallel conversion (digital pixels) offers a significantly higher dynamic range due to the exponential relationship between their charge handling capacity and pixel area, since the charge storage is in the digital domain. In DROICs with column parallel ADCs, signal chain resembles to an analog equivalent ROIC i.e charge is stored on an integration capacitor and charge handling capacity scales linearly with pixel area.…”

Section: Introductionmentioning

confidence: 99%

Cryogenic measurements of a digital pixel readout integrated circuit for LWIR

et al. 2015

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This paper presents and discusses the cryogenic temperature (77K) measurement results of a digital readout integrated circuit (DROIC) for a 32x32 long wavelength infrared pixel sensor array designed in 90nm CMOS process. The chip achieves a signal-to-noise ratio (SNR) of 58dB with a charge handling capacity of 2.03Ge-at cryogenic temperature with 1.3mW of power dissipation. The performance of the readout is discussed in terms of power dissipation, charge handling capacity and SNR considering the fact that the process library models are not optimized for cryogenic temperature operation of the Metal-Oxide-Semiconductor (MOS) devices. These results provide an insight to foresee the design confrontations due to non-optimized device models for cryogenic temperatures particularly for short channel devices

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Sigma-delta column-wise A/D conversion for cooled ROIC

Cited by 19 publications

References 0 publications

A low-power continuous-time incremental 2nd-order-MASH ΣΔ-modulator for a CMOS imager

A low-power continuous-time incremental 2nd-order-MASH ΣΔ-modulator for a CMOS imager

A 13-bit, low-power, compact ADC suitable for sensor applications

Cryogenic measurements of a digital pixel readout integrated circuit for LWIR

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