I For today's multi-million transistor designs, existing design verijication techniques cannot guarantee that first silicon 1 is designed error free. Therefore, techniques ate necessary to eflciently debug firstsilicon. In this article, we present a methodology for debugging multiple clock domain systems-on-a-chip. In addition to scan chains, a set of Design-for-Debug modules is 1 designed into an IC to make it debuggable. bebugger tool sofhvare interacts with the on-chip DjD to make the debug features available from a workstation.