Silicon Selective Epitaxial Growth and Electrical Properties of Epi/Sidewall Interfaces

Ishitani, Akihiko; Kitajima, Hiroshi; Endo, Nobuhiro; Kasai, N.

doi:10.1143/jjap.28.841

Cited by 31 publications

(18 citation statements)

References 17 publications

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“…However, as compared to the equilibrium shape of crystals, faceting during deposition or growth is a much more complex mechanism that relies on material properties and morphological configurations but also on process conditions. In silicon technology, faceting has been reported for a long time in epitaxy and especially in selective epitaxial growth (SEG) [2][3][4][5][6]. Si/SiGe epitaxial growths (epi) are of a great interest in Si-based technologies as they allow the fabrication of heterostructure bipolar transistors (HBT) and the development of the new CMOS architectures such as double gate or gate all around CMOS, silicon on nothing (SON), fully-depleted silicon on insulator (SOI)….…”

Section: Introductionmentioning

confidence: 99%

Facet Propagation in Si and SiGe Epitaxy or Etching

Dutartre

Talbot²,

Loubet³

2006

ECS Trans.

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The facets propagation during silicon and SiGe epitaxial growth has been studied in terms of morphology and kinetics. In a similar way the faceting effects during chemical etching of monocrystalline silicon have been examined. In both cases, the appearance of certain facets in certain experimental conditions have been explained on the basis of activation energies of the growth kinetics of the main high density crystal planes.

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Section: Introductionmentioning

confidence: 99%

Facet Propagation in Si and SiGe Epitaxy or Etching

Dutartre

Talbot²,

Loubet³

2006

ECS Trans.

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“…SEG obtained using the ͓100͔-oriented edges has much less stacking faults and crystal facets than those produced using other edge orientations. 11 The wafer is then placed in a standard reduced pressure chemical vapor deposition epitaxial reactor. A high temperature hydrogen bake is employed to remove the native oxide from the seed window.…”

Section: Unique Methods To Electrically Characterize a Single Stackingmentioning

confidence: 99%

Unique method to electrically characterize a single stacking fault in silicon-on-insulator metal–oxide–semiconductor field-effect transistors

Yang

Neudeck

Denton

2000

Applied Physics Letters

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Articles you may be interested inModeling and direct extraction of band offset induced by stress engineering in silicon-on-insulator metal-oxidesemiconductor field effect transistors: Implications for device reliability Strain and electrical characterization of metal-oxide-semiconductor field-effect transistor fabricated on mechanically and thermally transferred silicon on insulator filmsComparison of oxide breakdown progression in ultra-thin oxide silicon-on-insulator and bulk metal-oxidesemiconductor field effect transistors Electrical effects of a single stacking fault on fully depleted thin-film silicon-on-insulator P-channel metal-oxide-semiconductor field-effect transistors

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“…Facet generation is a kind of natural phenomenon on crystal growth, depending on several factors such as SEG condition, neighboring dielectric materials, pattern directions, etc. 5,6,15 In LPCVD system, facets are easy to form under the low ESR condition, where the dynamic force equilibrium can be reached among surface energies of SEG growing planes and neighboring insulators. Therefore, SEG facets were much enhanced in the last of this one-step growing conditions.…”

Section: A Selective Epitaxial Growth Plug Processmentioning

confidence: 99%