2004
DOI: 10.1063/1.1823018
|View full text |Cite
|
Sign up to set email alerts
|

Simulation of gate lag and current collapse in gallium nitride field-effect transistors

Abstract: Results of two-dimensional numerical simulations of gate lag and current collapse in GaN heterostructure field-effect transistors are presented. Simulation results clearly show that current collapse takes place only if an enhanced trapping occurs under the gate edges. Hot electrons play an instrumental role in the collapse mechanism. The simulation results also link the current collapse with electrons spreading into the buffer layer and confirm that a better electron localization (as in a double heterostructur… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
4
1

Citation Types

2
30
0

Year Published

2007
2007
2014
2014

Publication Types

Select...
7
1
1

Relationship

0
9

Authors

Journals

citations
Cited by 51 publications
(32 citation statements)
references
References 6 publications
2
30
0
Order By: Relevance
“…16,17 However, current collapse effects observed in most of the GaN-based transistors not only degrade microwave output performance but also impede reliable operation of the GaN-based power devices. 9,18 Previous numerical simulation work 18,19 has demonstrated that the significant current collapse effect, due to the charge trapping at the GaN bulk, degrades the device performance under radio frequency ͑RF͒ operations. The trapped charges may accumulate at the drain-side gate edge, where the electric field significantly changes and gate-voltage-dependent strain is induced.…”
Section: Introductionmentioning
confidence: 99%
See 1 more Smart Citation
“…16,17 However, current collapse effects observed in most of the GaN-based transistors not only degrade microwave output performance but also impede reliable operation of the GaN-based power devices. 9,18 Previous numerical simulation work 18,19 has demonstrated that the significant current collapse effect, due to the charge trapping at the GaN bulk, degrades the device performance under radio frequency ͑RF͒ operations. The trapped charges may accumulate at the drain-side gate edge, where the electric field significantly changes and gate-voltage-dependent strain is induced.…”
Section: Introductionmentioning
confidence: 99%
“…Identifying the essential physical mechanisms, which are responsible for particular effects of the MOS-HEMT's electrical behavior by means of simulation, allows pushing ahead the further development of the MOS-HEMT's. Although several numerical simulation studies [18][19][20][21][22][23] have been made on the GaN-based HEMTs, few works give a full consideration on GaN-based MOS-HEMTs and their related issues on polarization-induced charges and defectinduced traps at all of the interfaces. In addition, processrelated trap levels of bulk traps measured from experiments have not been taken into account.…”
Section: Introductionmentioning
confidence: 99%
“…Trapping has been proposed to occur by leakage from the gate into either the AlGaN barrier layer or onto the semiconductor surface [4], or by trapping of hot electrons into bulk traps [5,6]. The process is exacerbated by the high operational drain bias voltages in many GaN applications, which results in a large electric field at the drain side of the gate edge.…”
Section: Introductionmentioning
confidence: 99%
“…Trapping centers are cons idered to be the rna in cause of the parasitic effects. A lot of efforts have been dedicated into the investigation of trapping phenomena [4][5][6][7][8][9][10][11][12]. The tum-on pulse transient tests and simulation with surface traps were carried out in [3][4].…”
Section: Introductionmentioning
confidence: 99%