Single-Event Latch-Up: Increased Sensitivity From Planar to FinFET

Karp, James; Hart, Michael J.; Maillard, Pierre; Hellings, Geert; Linten, Dimitri

doi:10.1109/tns.2017.2779831

Cited by 29 publications

(10 citation statements)

References 13 publications

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“…2(c)], is still significant and exhibits complex responses to device design. As suggested in [50], SEL depends on parameters that do not always shrink along with device scaling, such as the dimension of wells and the depth of Shallow-Trench Isolation (STI). Hence, SEL is not addressed here-A literature survey, however, suggests that CMOS digital ICs generally become less sensitive to SEL along with the scaling of power supply voltage ( DD ) [51,Fig.…”

Section: A Tested Sees and Devicesmentioning

confidence: 99%

Scaling Trends of Digital Single-Event Effects: A Survey of SEU and SET Parameters and Comparison With Transistor Performance

Kobayashi

2021

IEEE Trans. Nucl. Sci.

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Section: A Tested Sees and Devicesmentioning

confidence: 99%

Scaling Trends of Digital Single-Event Effects: A Survey of SEU and SET Parameters and Comparison With Transistor Performance

Kobayashi

2021

IEEE Trans. Nucl. Sci.

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“…As discussed above, the SEL rates seen in DB5 could be eliminated by migrating back to Ultrascale FPGAs with a 20 nm TMSC planar technology, where SELs have not been observed [6]. One disadvantage of this migration from the KU+ architecture to the KU architecture is that the SEU rate is expected to increase by a factor of approximately 16 [5].…”

Section: Redesigning the Daughterboardmentioning

confidence: 99%

A Revised Version of the ATLAS Tile Calorimeter Link Daughterboard for the HL-LHC

Santurio

Silverstein

Böhm

et al. 2021

IEEE Trans. Nucl. Sci.

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The ATLAS Tile Calorimeter (TileCal) readout link and control Daughter Board (DB) is the central on-detector hub of the new TileCal electronics upgrade for the high-luminosity Large Hadron Collider (HL-LHC). The DB, which has undergone gradual redesigns during development, provides the connection between the on-and off-detector electronics via bi-directional fiber optic links. Two CERN-developed, radiation hard GBTx ASICs receive LHC timing signals and configuration commands through 4.8 Gbps downlinks, which are in turn propagated to the front-end through Xilinx Kintex Ultrascale FPGAs. The Kintex FPGAs also continuously perform real-time readout and transmission of digitized Photomultiplier (PMT) samples, Detector Control System signals and monitoring data through redundant pairs of 9.6 Gbps uplinks. The DB design aims at minimizing single points of failure, and improving performance and reliability of the board. Apart from the GBTx devices, the DB design relies on radiation-qualified Commercial off-theshelf (COTS) components. Mitigation of radiation-induced Single Event Upsets (SEU) in the FPGAs is performed by a combination of the Xilinx Soft Error Mitigation (SEM) utility and Triple Mode Redundancy (TMR) schemes in the FPGA firmware. Data integrity is protected through Forward Error Correction (FEC) in the downlinks and Cyclic Redundancy Check (CRC) error verification in the redundant uplinks. This paper presents the latest revision of the DB (version 6), a redesign that addresses Single Event Latch-up (SEL) behavior observed in the Kintex Ultrascale+ FPGAs used in the previous revision, and features a more robust power circuitry combined with an improved current monitoring scheme, enhanced performance of the ADC read-out, and improved timing performance.

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“…As discussed above, the SEL rates seen in DB5 could be eliminated by migrating back to Ultrascale FPGAs with a 20-nm planar technology (TSMC), where SELs have not been observed [6]. One disadvantage of this migration from the KU+ architecture to the KU architecture is that the SEU rate is expected to increase by a factor of approximately 16 [5].…”

Section: Redesigning the Dbmentioning

confidence: 99%

A revised version of the ATLAS Tile Calorimeter link Daughterboard for the HL-LHC

Santurio

Silverstein

Böhm

et al. 2020

2020 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)

View full text Add to dashboard Cite

The ATLAS Tile Calorimeter (TileCal) readout link and control daughterboard (DB) is the central on-detector hub of the new TileCal electronics upgrade for the high-luminosity large hadron collider (HL-LHC). The DB, which has undergone gradual redesigns during development, provides the connection between the on-and off-detector electronics via bidirectional fiber-optic links. Two CERN-developed, radiation hard GBTx application specified integrated circuits (ASICs) receive LHC timing signals and configuration commands through 4.8-Gb/s downlinks, which are in turn propagated to the front end through Xilinx Kintex Ultrascale field-programmable gate arrays (FPGAs). The Kintex FPGAs also continuously perform real-time readout and transmission of digitized photomultiplier (PMT) samples, detector control system (DCS) signals, and monitoring data through redundant pairs of 9.6-Gb/s uplinks. The DB design aims at minimizing single points of failure and improving the performance and reliability of the board. Apart from the GBTx devices, the DB design relies on radiation-qualified commercial off-the-shelf (COTS) components. Mitigation of radiationinduced single-event upsets (SEUs) in the FPGAs is performed by a combination of the Xilinx soft error mitigation (SEM) controller and triple-mode redundancy (TMR) schemes in the FPGA firmware. Data integrity is protected through forward error correction (FEC) in the downlinks and cyclic redundancy check (CRC) error verification in the redundant uplinks. This article presents the latest revision of the DB (version 6), a redesign that addresses single-event latch-up (SEL) behavior observed in the Kintex Ultrascale+ FPGAs used in the previous revision, and features a more robust power circuitry combined with an improved current monitoring scheme, enhanced performance of the analog-to-digital converter (ADC) read-out, and improved timing performance.

show abstract

Single-Event Latch-Up: Increased Sensitivity From Planar to FinFET

Cited by 29 publications

References 13 publications

Scaling Trends of Digital Single-Event Effects: A Survey of SEU and SET Parameters and Comparison With Transistor Performance

Scaling Trends of Digital Single-Event Effects: A Survey of SEU and SET Parameters and Comparison With Transistor Performance

A Revised Version of the ATLAS Tile Calorimeter Link Daughterboard for the HL-LHC

A revised version of the ATLAS Tile Calorimeter link Daughterboard for the HL-LHC

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