2004
DOI: 10.1109/tvlsi.2004.826198
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Sleep switch dual threshold Voltage domino logic with reduced standby leakage current

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Cited by 70 publications
(24 citation statements)
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“…The subthreshold-leakage power consumed by the original and dual-VT multiplier with and without time borrowing was measured for six different input vectors (given in Table 3), at a temperature of 110 using spice simulations. These are standard input vectors which have been used for comparing the efficiency of leakage reduction techniques in arithmetic units [8].…”
Section: Simulation Resultsmentioning
confidence: 99%
“…The subthreshold-leakage power consumed by the original and dual-VT multiplier with and without time borrowing was measured for six different input vectors (given in Table 3), at a temperature of 110 using spice simulations. These are standard input vectors which have been used for comparing the efficiency of leakage reduction techniques in arithmetic units [8].…”
Section: Simulation Resultsmentioning
confidence: 99%
“…The logic of a dynamic gate is utilized only during the evaluation phase. Thus the critical path of a dynamic circuit is always the evaluation phase [4,7]. MITH-Dyn has been proposed taking this fact into consideration.…”
Section: Finfet Based Circuit Designmentioning
confidence: 99%
“…The scaling of V th results in increased sub-threshold leakage current. In earlier days the contribution of leakage power in dynamic circuits were negligible, but recent works [7][8][9] shows that the component of leakage power in dynamic circuits cannot be neglected and they contribute to almost 40% in the total power consumption. The switching power of dynamic circuits can be reduced using techniques proposed in [3,10] such as clock gating.…”
Section: Introductionmentioning
confidence: 99%
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