Soft defect localization (SDL) in integrated circuits using laser scanning microscopy

Bruce, Mike; Bruce, Victoria J.; Eppes, David; Wilcox, Jacob; Cole, Edward I.; Tangyunyong, Paiboon; Hawkins, C.F.; Ring, Rose

doi:10.1109/leos.2003.1252974

Cited by 20 publications

(7 citation statements)

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“…For the laser to have a detectable impact on circuit behavior, the chip must be operated in a marginal condition [15,16], usually by acquiring a voltage-frequency shmoo plot of the failing part and operating the chip near the pass/fail 2D.1.4…”

Section: ) Dynamic Laser Stimulationmentioning

confidence: 99%

Comparison of applications of laser probing, laser-induced circuit perturbation and photon emission for failure analysis and yield enhancement

Kasapi

Liao

et al. 2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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The transparency of the silicon substrate in CMOS circuits to near infra-red light has enabled a rich variety of optical techniques for observing and modifying circuit behavior. The main classes of optical analysis techniques are photon emission, laser-induced circuit perturbation, and laser probing. Recent innovations in laser probing present significant new opportunities for failure analysis and yield enhancement. This paper presents several case studies with particular emphasis on how the new laser probing techniques complement and extend the established approaches.

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Section: ) Dynamic Laser Stimulationmentioning

confidence: 99%

Comparison of applications of laser probing, laser-induced circuit perturbation and photon emission for failure analysis and yield enhancement

Kasapi

Liao

et al. 2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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“…9). A systematic overview on the LS at dynamic circuit operation like in (Bruce et al, 2002) for static techniques is nor yet available, so in Table 1 some of the techniques seem to be overlapping and some possible options have not been published yet.…”

Section: Laser Stimulationmentioning

confidence: 99%

Physical IC debug – backside approach and nanoscale challenge

et al. 2008

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Abstract. Physical analysis for IC functionality in submicron technologies requires access through chip backside. Based upon typical global backside preparation with 50-100 µm moderate silicon thickness remaining, a state of the art of the analysis techniques available for this purpose is presented and evaluated for functional analysis and layout pattern resolution potential. A circuit edit technique valid for nano technology ICs, is also presented that is based upon the formation of local trenches using the bottom of Shallow Trench Isolation (STI) as endpoint for Focused Ion Beam (FIB) milling. As a derivative from this process, a locally ultra thin silicon device can be processed, creating a back surface as work bench for breakthrough applications of nanoscale analysis techniques to a fully functional circuit through chip backside. Several applications demonstrate the power and potential of this new approach.

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“…With the current production technology node at 14 nm (based on fin width), identifying and understanding individual finFETs is a burgeoning field. Defects in finFETs are currently identified using electrical, optical, or thermal techniques such as soft defect localization using a scanning optical microscope (Bruce et al, 2003;Phang et al, 2004), infrared (IR)-based techniques, due to Si being transparent to IR wavelengths (Nikawa et al, 1999;Phang et al, 2004) and scanning spread resistance microscopy (Zhang et al, 2007;Hayase et al, 2012). Although these techniques can tell the pass or fail state of each transistor and a localized region where the FETs are good or bad, the relationship between device failure and structural or concentration anomalies is still missing.…”

Section: Introductionmentioning

confidence: 99%

Three-Dimensional Nanoscale Mapping of State-of-the-Art Field-Effect Transistors (FinFETs)

et al. 2017

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The semiconductor industry has seen tremendous progress over the last few decades with continuous reduction in transistor size to improve device performance. Miniaturization of devices has led to changes in the dopants and dielectric layers incorporated. As the gradual shift from two-dimensional metal-oxide semiconductor field-effect transistor to three-dimensional (3D) field-effect transistors (finFETs) occurred, it has become imperative to understand compositional variability with nanoscale spatial resolution. Compositional changes can affect device performance primarily through fluctuations in threshold voltage and channel current density. Traditional techniques such as scanning electron microscope and focused ion beam no longer provide the required resolution to probe the physical structure and chemical composition of individual fins. Hence advanced multimodal characterization approaches are required to better understand electronic devices. Herein, we report the study of 14 nm commercial finFETs using atom probe tomography (APT) and scanning transmission electron microscopy-energy-dispersive X-ray spectroscopy (STEM-EDS). Complimentary compositional maps were obtained using both techniques with analysis of the gate dielectrics and silicon fin. APT additionally provided 3D information and allowed analysis of the distribution of low atomic number dopant elements (e.g., boron), which are elusive when using STEM-EDS.

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Soft defect localization (SDL) in integrated circuits using laser scanning microscopy

Cited by 20 publications

References 0 publications

Comparison of applications of laser probing, laser-induced circuit perturbation and photon emission for failure analysis and yield enhancement

Comparison of applications of laser probing, laser-induced circuit perturbation and photon emission for failure analysis and yield enhancement

Physical IC debug – backside approach and nanoscale challenge

Three-Dimensional Nanoscale Mapping of State-of-the-Art Field-Effect Transistors (FinFETs)

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