Soft Error Hardened Memory Design for Nanoscale Complementary Metal Oxide Semiconductor Technology

Guo, Jifeng; Xiao, Liyi; Wang, Tianqi; Liu, Shanshan; Wang, Xu; Mao, Zhigang

doi:10.1109/tr.2015.2410275

Cited by 38 publications

(12 citation statements)

References 25 publications

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“…The highlevel structure is a column in a cache memory as proposed and described in [19], [20]. Necessary signal drivers and wire capacitances are added to the bitlines (BL and BLB) and wordlines (WL) based on the SRAM layout sizes drawn in [21], [25], [7], [3]. Since these are the same for all four cells structures, the comparison between the cells are just.…”

Section: Design Methodology and Simulation Resultsmentioning

confidence: 99%

Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications

Seyedi

Aunet

Kjeldsberg

2019

2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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In the electronics space industry, memory cells are one of the main concerns, especially in term of reliability, since radiation particles may hit cell nodes and disturb the state of the cell, possibly causing fatal errors. In this paper we propose the Nwise SRAM cell, an area-efficient and highly reliable radiation hardened memory cell for use in high-density memories for space applications. Simulations confirm that the proposed Nwise cell is fully tolerant to single event upsets (SEU) in any one of its nodes regardless of upset polarity. Meanwhile, compared with the RHBD-10T cell, the latest area-efficient radiation hardened memory cell, it has higher robustness: the minimum critical charge of Nwise is 4.1× 4.1× 4.1× higher than the minimum critical charge of the RHBD-10T cell. It also shows 23% and 12% improvements in read and write static noise margin (SNM). Furthermore, compared with RHBD-10T, up to 18.4% and 7.0% power savings are obtainable during write and read operations respectively. Nwise is about 2.28× × × faster than RHBD-10T during the more frequent read operation, with a similar penalty in write time. Finally, Nwise is the first proposed high density and reliable radiation hardened memory cell that has been designed using the 28nm FD-SOI technology node.

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Section: Design Methodology and Simulation Resultsmentioning

confidence: 99%

Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications

Seyedi

Aunet

Kjeldsberg

2019

2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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“…If a radiation particle strikes the drain surroundings of an NMOS transistor, it produces either a '1'→'0' or a '0'→'0', depending on the initially stored value [2]. On the other hand, the drain surroundings of a PMOS transistor, if struck by radiation, generates a transient pulse of either '1'→'1' or '0'→'1' [22]. As the '0'-storing storage node (QB) of EDP12T is surrounded by the drain terminal of only NMOS transistors (Fig.…”

Section: B Seu Recovery Analysismentioning

confidence: 99%

Energy-Efficient Dual-Node-Upset-Recoverable 12T SRAM for Low-Power Aerospace Applications

Pal

Chowdary

et al. 2023

IEEE Access

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With technology scaling, transistor sizing, as well as the distance between them, is decreasing rapidly, thereby reducing the critical charge of sensitive nodes. This reduction makes SRAM cells, used for aerospace applications, more susceptible to radiation as it can cause single-event upsets (SEUs) and also single-event multi-node upsets (SEMNUs). This article presents an energy-efficient dual-node-upsetrecoverable 12T SRAM cell for low-power aerospace applications, EDP12T, in 65-nm CMOS technology. The proposed cell mitigates SEUs as well as SEMNUs. To judge the relative performance of EDP12T, a comparative study is made between it and other radiation-hardened cells, RHM12T, QUCCE12T, QUATRO12T, RHD12T, SRRD12T, RHPD12T, RSP14T, LWS14T, SAR14T, and S8P4N16T. EDP12T can recover from SEUs injected at all the sensitive nodes and SEMNUs that have occurred at its internal nodepair. In addition, EDP12T also exhibits better write performance than most of the comparison cells. Among all the cells for comparison, EDP12T dissipates the lowest hold power, except RHM12T. In addition to these, it consumes the least energy during write mode and also consumes lower energy than most of the comparison cells during read mode. It also exhibits 1.08×/ 1.17×/ 1.37×/ 1.56×/ 2.32× higher read stability than S8P4N16T/ RHPD12T/ QUCCE12T/ QUATRO12T/ LWS14T. All these aforementioned improvements are obtained by the proposed cell while consuming 1.03×/ 1.06×/ 1.07×/ 1.08×/ 1.14×/ 1.43× lower area than SAR14T/ RHD12T/ S8P4N16T/ RSP14T/ LWS14T/ RHPD12T. However, these advantages come with a slight penalty in read delay.INDEX TERMS SRAM cell, read energy, write energy, hold power, read stability, write ability, single-event upset (SEU), single-event multi-node upset (SEMNU), critical charge, aerospace applications.

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“…Authors in [17] propose a low-power radiation hardened 12T cell based on both circuit level and layout-level SEU mitigation techniques. The design is derived from the PS cell proposed in [16], and by adding two stacked NMOS transistors, the circuit can tolerate SEUs at any sensitive nodes regardless of upset polarity.…”

Section: ) Previous Cell Designs That Cannot Provide Seu Tolerancementioning

confidence: 99%

Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements

2022

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SRAM cells are widely used to design memory blocks of, e.g., caches, register files, and translation lookaside buffers. Depending on the SRAM application, the design requirements are different. For instance, in space applications, alongside energy efficiency, reliability is a main issue since the system is launched into space with a limited energy budget and stay exposed to high doses of radiation strikes for a long time. The Nwise cell has recently been proposed by the authors of this paper as the first highly reliable radiation hardened SRAM cell designed with 28nm FD-SOI. In this paper, inspired from the Nwise cell, we introduce another highly reliable radiation hardened SRAM cell, the Pwise cell, which is also designed with 28nm FD-SOI technology. Through comprehensive simulations of state-of-the-art cells, we show that both the Nwise and Pwise cells are competitive radiation hardened SRAMs to use in different memory blocks for space applications: (1) Both have the highest level of Single Event Upsets (SEU) tolerance capability for the temperature range deployed in space applications; further, both have the highest level of the tolerance capability to Multi Event Upsets (MEU). ( 2) Compared with the simulated cells that have comparable tolerance capability, the Nwise cell has low read delay and read power consumption, hence, it can be a good choice for space application cache designs, while the Pwise cell can be a proper candidate for space application register file designs since it has low write and read delay.

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Soft Error Hardened Memory Design for Nanoscale Complementary Metal Oxide Semiconductor Technology

Cited by 38 publications

References 25 publications

Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications

Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications

Energy-Efficient Dual-Node-Upset-Recoverable 12T SRAM for Low-Power Aerospace Applications

Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements

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