Soft error rate increase for new generations of SRAMs

Abstract

We report on enhanced susceptibility for neutron-induced soft errors from accelerated testing of static random access memories (SRAMs), performed at Los Alamos National Laboratory. This enhancement is per bit of memory.

Characterization of soft errors caused by single event upsets in CMOS processes

“…In [79], the neutron SER in 6T cells increased by 2x per generation from 0.25m to 0.14m. Granlund et al [80] found that the SER decreased by 2x from 0.5m to 0.25m node and then increased by 4x from 0.25m to 0.14m. This nonmonotonic trend was explained by a disproportionate scaling of Q CRIT with respect to collection efficiency.…”

Design of a soft-error robust microprocessor

“…For instance, the neutron flux at 12 km (~40000 ft) altitude is around 300 times higher than at sea level and at 20 km (~60000 ft) it has its maximum peak. For this reason, integrated circuits operating at aircraft altitudes are more susceptible to faults induced by such particles than at ground level (NORMAND, 1996-b;GRANLUND;GRANBOM;OLSSON, 2003).…”

“…Others show the SER increase in the new technology generations of ICs due to the scaling and technology trends (HAZUCHA el al, 2003;GRANLUND;GRANBOM;OLSSON, 2003;BORKAR, 2005).…”

A New Asymmetric SRAM Cell to Reduce Soft Errors and Leakage Power in FPGA

“…Soft errors in CMOS circuits occur due to charged particle strikes which are present as cosmic rays in the atmosphere and α-particles within the chip itself [1], [2], [3], [4], [5]. Soft errors in modern VLSI circuits are a major reliability concern.…”