SOI four-gate transistors (G/sup 4/-FETs) for high voltage analog applications

Chen, S.; Vandersand, J.; Blalock, Benjamin J.; Akarvardar, K.; Cristoloveanu, S.; Mojarradi, Mohammad

doi:10.1109/esscir.2005.1541622

Cited by 3 publications

(4 citation statements)

References 8 publications

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“…The HV differential amplifier in [5] is used in a non-inverting unity gain configuration to an input of 1 V peak-to-peak square wave of 1 kHz frequency. The circuit has been simulated with the developed model and the result in Fig.…”

Section: Results From G 4 Fet Circuit Simulationmentioning

confidence: 99%

“…The second circuit is a high voltage (HV) differential amplifier first demonstrated in [5], which is simulated using a SPICE simulator. Compared to regular MOSFETS, G 4 FETs can sustain much higher voltages in the same process technology.…”

Section: Results From G4fet Circuit Simulationmentioning

confidence: 99%

“…Absolute value of mean relative error, % (6,4,4,4) 0.7346 (8,4,4,4) 0.7091 (10,4,4,4) 0.7067 (6,4,5,5) 0.5888 (8,4,5,5) 0.5734 (10,4,5,5) 0.5728 Table 6. Here, the order of V JG and V TG are varied to show the effect of order on model accuracy.…”

Section: Experimental Data From P-channel G 4 Fet (Device 4)mentioning

confidence: 99%

“…As a result of this combination of excellent properties, higher gate count, and unique configuration, G 4 FET technology has the potential for new circuit opportunities for analogue, RF, mixedsignal, and digital applications. Already experimentally demonstrated applications include analogue multipliers [4], highvoltage current mirrors and differential amplifiers [5], LC oscillators and Schmitt trigger circuits using negative differential resistance (NDR) [6], G 4 FET inspired multiple state electrostatically formed nanowires for threshold logic functions [7,8] and high-sensitivity gas sensing and femtomolar bio-marker detection [9,10] temperature compensated voltage references [11], and innovative digital applications [12,13]. A very promising potential application is the formation of quantum wire in depletionall-around action when the vertical MOS gates and lateral JFET gates are used simultaneously to create a conducting channel surrounded by depletion regions [14].…”

Section: Introductionmentioning

confidence: 99%

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DC modelling of SOI four‐gate transistor (G ⁴ FET) for implementation in circuit simulator using multivariate regression polynomial

Hasan

Islam

2018

IET Circuits, Devices & Systems

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An efficient numerical model of silicon-on-insulator (SOI) four-gate transistors (G 4 FET) and its implementation in circuit simulator is presented here. A set of available data for different operating conditions is used to empirically determine the parameters of this model and a different set of test data is used to verify its predictive accuracy. This DC model is used to express the drain current as a single multivariate regression polynomial with its validity spanning across different possible operating regions as long as the chosen independent variables lie within the range of data set used to develop the model. The continuity of the polynomial model and its derivatives makes it particularly suitable for implementation in a circuit simulator. Models for both n-channel and p-channel G 4 FETs have been developed and validated using TCAD and experimental data and are successfully implemented in SPICE simulator for simulating two experimentally demonstrated G 4 FET circuits.

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Section: Results From G 4 Fet Circuit Simulationmentioning

confidence: 99%

Section: Results From G4fet Circuit Simulationmentioning

confidence: 99%