Sources of overlay error in double patterning integration schemes

Abstract

With the planned introduction of double patterning techniques, the focus of attention has been on tool overlay performance and whether or not this meets the required overlay for double patterning. However, as we require tighter and tighter overlay performance, the impact of the selected integration strategy plays a key part in determining the achievable overlay performance. Very little attention has been given at this time to the impact of for example deposition steps, oxidation steps, CMP steps and the impact that they have on wafer deformation and therefore degraded overlay performance, which directly reduces the available overlay budget. Also, selecting the optimum alignment strategy to follow, either direct or indirect alignment, plays an important part in achieving optimum overlay performance. In this paper we investigate the process impact of various double patterning integration strategies and attempt to show the importance of selecting the right strategy with respect to achieving a manufacturable double patterning process. Furthermore, we report a methodology to minimize process overlay by modelling the non-linear grids for process induced wafer deformation and demonstrate best achievable overlay by feeding this information back to the relevant process steps.

ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration

“…Wakamoto et al [17] propose an on-the-fly overlay error correction mechanism. Laidler et al [18] identify error sources in overlay. Kim et al [19] present silicon results of 193nm double patterning using negative-tone photoresist.…”

“…The second mask for a given layer is aligned with respect to the first mask of the same layer as shown in Figure 1(b). While this alignment methodology reduces standard deviation of overlay errors by about 30% (1 − 1/ √ 2) compared with IA, it brings additional difficulties in optimizing the process parameters for the second mask alignment to the first mask [18].…”

Comprehensive Performance Analysis of Interconnect Variation by Double and Triple Patterning Lithography Processes

“…The critical dimension (CD), or metal width, or metal height (H) between two adjacent lines (or three parallel lines in TPL) vary as the result of two (or three) separate lithography and etching processes [13]. In addition, overlay (OL) errors occur because of the misalignment between two or three consecutive lithoetch processes [9,14,15]. The OL errors cause nonuniform spacing between neighboring interconnect lines and are attributed to the change in the coupling capacitance.…”

“…The performance impact of RC delay and coupling capacitance on local interconnects by several advanced patterning options such as LELE, spacer-defined double patterning (SDDP), and extreme ultraviolet (EUV) lithography were analyzed in [13]. In [14], the process impacts of various DPL strategies were investigated, and the authors proposed a methodology to minimize the OL. A full-chip-level comparison between OL error and interconnect variations by the DPL process has been conducted in [15].…”

Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology

“…2(b). Nevertheless, stitch insertion may cause yield loss due to overlay errors [16]. Stitch minimization thus becomes an important issue in DPT.…”